Smart Home Audio(325)


The M2351CIAAE microcontroller series is powered by Arm® Cortex®-M23 core with TrustZone® for Armv8-M architecture, which elevates the traditional firmware security to a new level of robust software security.

The low-power M2351 series microcontroller operates at up to 64 MHz frequency, with up to 512 KB embedded Flash memory in dual bank mode, supporting secure OTA (Over-The-Air) firmware update and up to 96 KB embedded SRAM. Furthermore, the M2351 series also provides high-performance connectivity peripheral interfaces such as UART, SPI, I²C, GPIOs, USB and ISO 7816-3 for smart card reader. Its secure and efficient power management features strengthen the innovation of IoT security. 

Key Features:

Security Core

  • Arm® Cortex®-M23 core delivering 0.95 DMIPS per MHz
  • TrustZone® for ARM®v8-M
  • 32-bit Single-cycle hardware multiplier and 32-bit 17-cycle hardware divider
  • Up to 8 regions MPU_NS (for non-secure world)
  • Up to 8 regions MPU_S (for secure world)
  • 8 Security Attribution Unit (SAU) memory regions


  • Up to 512 KB of dual bank Flash memory. Dual bank Flash memory allows read-while-write programming
  • Up to 96 KB SRAM, first 32KB SRAM with hardware parity check
  • 4 KB Flash for user program loader (LDROM)
  • 2 KB OTP for general-purpose control use, (2 KB data + 1 KB lock bit) easy for PLM (Product Lifecycle Management) implementation
  • 32 KB Secure Boot ROM
  • ISP/ICP/IAP programming
  • External Bus Interface (EBI) supports maximum external address space of 1 M Bytes, up to 3 chip selects and 8/16-bit external data bus

Power management

Normal run: 97 μA/MHz (LDO);
    45 μA/MHz (DC-DC)

Idle: 36 μA/MHz (CPU clock disabled, LDO);
    17μA/MHz (CPU clock disabled, DC-DC)
  • Power-down: 20 μA
  • Standby power-down: 3.0 μA
  • Deep Power-down: 4.0 μA (with VBAT)
  • Deep Power-down: 1.5 μA (without VBAT)
  • VBAT supply for RTC:  2.5 μA (80 bytes spare registers)

Crypto and Security

  • True random number generator (TRNG)
  • AES 256/ SHA 384/ 3-DES/ DES
  • The ECC accelerator is a fully compliant implementation for the prime field GF(p) and binary field GF(2m) algorithms. The prime field GF(p) supports up to NIST P-521. The binary field GF(2m) supports up to NIST B-571 and NIST K-163, K-233, K-283, K-409and K-571.
  • CRC calculation unit

Communication interfaces

  • Up to 11 UART interfaces (up to 10.66 MHz), with up to 3 ISO-7816-3 interfaces, 6 RS-485, 6 IrDA and 2 LIN interfaces
  • Up to 5 I2C interfaces (up to 1 Mbps), with up to 3 I2C with SM Bus/ PM Bus
  • Up to 6 SPI interfaces (up to 64 MHz), with 3 I2S interfaces, additional 1 Quad-SPI interface
  • Up to 4 I2S interfaces, 3 I2S shared with 3 SPI
  • Secure Digital I/O (SDIO)(up to 50 MHz)

Advanced connectivity

  • USB 2.0 full speed OTG controller with on-chip PHY
  • One CAN interface up to 1 Mbps (CAN 2.0A and 2.0B standard)
  • Support crystal-less USB

Operating Characteristics

  • Running up to 64 MHz
  • Voltage range: 1.7V to 3.6 V
  • Temperature range: -40°C to +105°C
  • Selectable core power voltage levels: 1.26V, 1.2V in run and idle mode

Packages (RoHS)

  • WLCSP 49-pin


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