48 uint32_t u32MasterSlave,
50 uint32_t u32DataWidth,
53 if(u32DataWidth == 32)
71 CLK->APBCLK &= ~CLK_APBCLK_SPI0CKEN_Msk;
73 SYS->IPRST2 &= ~SYS_IPRST2_SPI0RST_Msk;
78 CLK->APBCLK &= ~CLK_APBCLK_SPI1CKEN_Msk;
80 SYS->IPRST2 &= ~SYS_IPRST2_SPI1RST_Msk;
85 CLK->APBCLK &= ~CLK_APBCLK_SPI2CKEN_Msk;
87 SYS->IPRST2 &= ~SYS_IPRST2_SPI2RST_Msk;
92 CLK->APBCLK &= ~CLK_APBCLK_SPI3CKEN_Msk;
94 SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk;
126 spi->
SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
153 uint32_t u32ClkSrc, u32Div = 0;
239 if(u32BusClock > u32ClkSrc)
240 u32BusClock = u32ClkSrc;
242 if(u32BusClock != 0 )
244 u32Div = (u32ClkSrc / u32BusClock) - 1;
251 spi->
CLKDIV = (spi->
CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
253 return ( u32ClkSrc / (u32Div+1) );
279 spi->
CTL &= ~SPI_CTL_FIFOM_Msk;
322 return (u32ClkSrc / (u32Div + 1));
377 spi->
CTL &= ~SPI_CTL_UNITIEN_Msk;
380 spi->
SSCTL &= ~SPI_SSCTL_SSTAIEN_Msk;
383 spi->
FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
386 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
389 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
392 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
412 spi->
CTL &= ~SPI_CTL_WKCLKEN_Msk;
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
#define SPI_SSCTL_SSACTPOL_Msk
#define SPI_FIFOCTL_RXOVIEN_Msk
#define SPI_CTL_UNITIEN_Msk
#define SPI_FIFOCTL_RXTH_Pos
#define SPI_FIFOCTL_TXTH_Msk
#define SPI_CTL_DWIDTH_Pos
#define SPI_CLKDIV_DIVIDER_Msk
#define SPI_FIFOCTL_TXTH_Pos
#define SPI_SSCTL_SSTAIEN_Msk
#define SPI_FIFOCTL_RXTOIEN_Msk
#define SPI_FIFOCTL_RXTHIEN_Msk
#define SPI_FIFOCTL_RXTH_Msk
#define SPI_FIFOCTL_TXFBCLR_Msk
#define SPI_CTL_FIFOM_Msk
#define SPI_FIFOCTL_TXTHIEN_Msk
#define SPI_FIFOCTL_RXFBCLR_Msk
#define SPI_SSCTL_AUTOSS_Msk
#define SPI_CTL_WKCLKEN_Msk
#define CLK_CLKSEL1_SPI2SEL_HXT
#define CLK_CLKSEL1_SPI0SEL_PLL
#define CLK_CLKSEL2_SPI3SEL_HXT
#define CLK_CLKSEL2_SPI3SEL_PLL
#define CLK_CLKSEL1_SPI2SEL_PLL
#define CLK_CLKSEL1_SPI0SEL_HCLK
#define CLK_CLKSEL2_SPI1SEL_PLL
#define CLK_CLKSEL1_SPI0SEL_HXT
#define CLK_CLKSEL1_SPI2SEL_HCLK
#define CLK_CLKSEL2_SPI3SEL_HCLK
#define CLK_CLKSEL2_SPI1SEL_HCLK
#define CLK_CLKSEL2_SPI1SEL_HXT
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
#define SYS_IPRST2_SPI3RST_Msk
#define SYS_IPRST2_SPI0RST_Msk
#define SYS_IPRST2_SPI1RST_Msk
#define SYS_IPRST2_SPI2RST_Msk
#define CLK_CLKSEL2_SPI1SEL_Msk
#define CLK_APBCLK_SPI3CKEN_Msk
#define CLK_APBCLK_SPI2CKEN_Msk
#define CLK_APBCLK_SPI0CKEN_Msk
#define CLK_PWRCTL_HIRC0EN_Msk
#define CLK_CLKSEL1_SPI0SEL_Msk
#define CLK_CLKSEL1_SPI2SEL_Msk
#define CLK_APBCLK_SPI1CKEN_Msk
#define CLK_CLKSEL2_SPI3SEL_Msk
#define CLK_CLKSEL0_HIRCSEL_Msk
#define CLK
Pointer to CLK register structure.
#define SPI1
Pointer to SPI1 register structure.
#define SYS
Pointer to SYS register structure.
#define SPI0
Pointer to SPI0 register structure.
#define SPI2
Pointer to SPI2 register structure.
#define SPI1_BASE
SPI1 register base address.
#define SPI2_BASE
SPI2 register base address.
#define SPI0_BASE
SPI0 register base address.
#define SPI3_BASE
SPI3 register base address.
#define SPI_FIFO_TIMEOUIEN_MASK
#define SPI_FIFO_RXOVIEN_MASK
#define SPI_FIFO_RXTHIEN_MASK
#define SPI_FIFO_TXTHIEN_MASK
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.