Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
Data Fields
LCD_T Struct Reference

#include <Nano1X2Series.h>

Data Fields

__IO uint32_t CTL
 
__IO uint32_t DISPCTL
 
__IO uint32_t MEM_0
 
__IO uint32_t MEM_1
 
__IO uint32_t MEM_2
 
__IO uint32_t MEM_3
 
__IO uint32_t MEM_4
 
__IO uint32_t MEM_5
 
__IO uint32_t MEM_6
 
__IO uint32_t MEM_7
 
__IO uint32_t MEM_8
 
uint32_t RESERVE0 [1]
 
__IO uint32_t FCR
 
__IO uint32_t FCSTS
 

Detailed Description

@addtogroup LCD LCD Controller(LCD)
Memory Mapped Structure for LCD Controller

Definition at line 5241 of file Nano1X2Series.h.

Field Documentation

◆ CTL

__IO uint32_t LCD_T::CTL

CTL

Offset: 0x00 LCD Control Register

Bits Field Descriptions
[0] EN LCD Enable
0 = LCD controller operation Disabled.
1 = LCD controller operation Enabled.
[3:1] MUX Mux Select
000 = Static.
001 = 1/2 duty.
010 = 1/3 duty.
011 = 1/4 duty.
100 = 1/5 duty.
101 = 1/6 duty.
110 = Reserved.
111 = Reserved.
Note: User does not need to set PD_H_MFP bit field, but only to set the MUX bit field to switch LCD_SEG0 and LCD_SEG1 to LCD_COM4 and LCD_COM5.
[6:4] FREQ LCD Frequency Selection
000 = LCD_CLK Divided by 32.
001 = LCD_CLK Divided by 64.
010 = LCD_CLK Divided by 96.
011 = LCD_CLK Divided by 128.
100 = LCD_CLK Divided by 192.
101 = LCD_CLK Divided by 256.
110 = LCD_CLK Divided by 384.
111 = LCD_CLK Divided by 512.
[7] BLINK LCD Blinking Enable
0 = Blinking Disabled.
1 = Blinking Enabled.
[8] PDDISP_EN Power Down Display Enable
The LCD can be programmed to be displayed or not be displayed at power down state by PDDISP_EN setting.
0 = LCD display Disabled ( LCD is put out) at power down state.
1 = LCD display Enabled (LCD keeps the display) at power down state.
[9] PDINT_EN Power Down Interrupt Enable
If the power down request is triggered from system management, LCD controller will execute the frame completely to avoid the DC component.
When the frame is executed completely, the LCD power down interrupt signal is generated to inform system management that LCD controller is ready to enter power down state, if PDINT_EN is set to 1.
Otherwise, if PDINT_EN is set to 0, the LCD power down interrupt signal is blocked and the interrupt is disabled to send to system management.
0 = Power Down Interrupt Disabled.
1 = Power Down Interrupt Enabled.

Definition at line 5288 of file Nano1X2Series.h.

◆ DISPCTL

__IO uint32_t LCD_T::DISPCTL

DISPCTL

Offset: 0x04 LCD Display Control Register

Bits Field Descriptions
[0] CPUMP_EN Charge Pump Enable
0 = Disabled.
1 = Enabled.
[2:1] BIAS_SEL Bias Selection
00 = Static.
01 = 1/2 Bias.
10 = 1/3 Bias.
11 = Reserved.
[4] IBRL_EN Internal Bias Reference Ladder Enable
0 = Bias reference ladder Disabled.
1 = Bias reference ladder Enabled.
[6] BV_SEL Bias Voltage Type Selection
0 = C-Type bias mode. Bias voltage source from internal bias generator.
1 = R-Type bias mode. Bias voltage source from external bias generator.
Note: The external resistor ladder should be connected to the V1 pin, V2 pin, V3 pin and VSS.
The VLCD pin should also be connected to VDD.
[10:8] CPUMP_VOL_SET Charge Pump Voltage Selection
000 = 2.7V.
001 = 2.8V.
010 = 2.9V.
011 = 3.0V.
100 = 3.1V.
101 = 3.2V.
110 = 3.3V.
111 = 3.4V.
[13:11] CPUMP_FREQ Charge Pump Frequency Selection
000 = LCD_CLK.
001 = LCD_CLK/2.
010 = LCD_CLK/4.
011 = LCD_CLK/8.
100 = LCD_CLK/16.
101 = LCD_CLK/32.
110 = LCD_CLK/64.
111 = LCD_CLK/128.
[16] Ext_C Ext_C Mode Selection
This mode is similar to C-type LCD mode, but the operation current is lower than C-type mode.
The control register setting is same with C-type mode except this bit is set to "1".
0 = Disable.
1 = Enable.
[18:17] Res_Sel R-Type Resistor Value Selection
The LCD operation current will be different when we select different R-type resistor value.
00 = 200K Ohm.
01 = 300K Ohm.
10 = Reserved.
11 = 400K Ohm.

Definition at line 5343 of file Nano1X2Series.h.

◆ FCR

__IO uint32_t LCD_T::FCR

FCR

Offset: 0x30 LCD frame counter control register

Bits Field Descriptions
[0] FCEN LCD Frame Counter Enable
0 = Disabled.
1 = Enabled.
[1] FCINTEN LCD Frame Counter Interrupt Enable
0 = Frame counter interrupt Disabled.
1 = Frame counter interrupt Enabled.
[3:2] PRESCL Frame Counter Pre-Scaler Value
00 = CLKframe/1.
01 = CLKframe/2.
10 = CLKframe/4.
11 = CLKframe/8.
[9:4] FCV Frame Counter Top Value
These 6 bits contain the top value of the Frame counter.

Definition at line 5530 of file Nano1X2Series.h.

◆ FCSTS

__IO uint32_t LCD_T::FCSTS

FCSTS

Offset: 0x34 LCD frame counter status

Bits Field Descriptions
[0] FCSTS LCD Frame Counter Status
0 = Frame counter value does not reach FCV (Frame Count TOP value).
1 = Frame counter value reaches FCV (Frame Count TOP value).
If the FCINTEN is s enabled, the frame counter overflow Interrupt is generated.
[1] PDSTS Power-Down Interrupt Status
0 = Inform system manager that LCD controller is not ready to enter power-down state until this bit becomes 1 if power down is set and one frame is not executed completely.
1 = Inform system manager that LCD controller is ready to enter power-down state if power down is set and one frame is executed completely

Definition at line 5547 of file Nano1X2Series.h.

◆ MEM_0

__IO uint32_t LCD_T::MEM_0

MEM_0

Offset: 0x08 LCD SEG3 ~ SEG0 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5361 of file Nano1X2Series.h.

◆ MEM_1

__IO uint32_t LCD_T::MEM_1

MEM_1

Offset: 0x0C LCD SEG7 ~ SEG4 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5379 of file Nano1X2Series.h.

◆ MEM_2

__IO uint32_t LCD_T::MEM_2

MEM_2

Offset: 0x10 LCD SEG11 ~ SEG8 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5397 of file Nano1X2Series.h.

◆ MEM_3

__IO uint32_t LCD_T::MEM_3

MEM_3

Offset: 0x14 LCD SEG15 ~ SEG12 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5415 of file Nano1X2Series.h.

◆ MEM_4

__IO uint32_t LCD_T::MEM_4

MEM_4

Offset: 0x18 LCD SEG19 ~ SEG16 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5433 of file Nano1X2Series.h.

◆ MEM_5

__IO uint32_t LCD_T::MEM_5

MEM_5

Offset: 0x1C LCD SEG23 ~ SEG20 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5451 of file Nano1X2Series.h.

◆ MEM_6

__IO uint32_t LCD_T::MEM_6

MEM_6

Offset: 0x20 LCD SEG27 ~ SEG24 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5469 of file Nano1X2Series.h.

◆ MEM_7

__IO uint32_t LCD_T::MEM_7

MEM_7

Offset: 0x24 LCD SEG31 ~ SEG28 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5487 of file Nano1X2Series.h.

◆ MEM_8

__IO uint32_t LCD_T::MEM_8

MEM_8

Offset: 0x28 LCD SEG35 ~ SEG32 data

Bits Field Descriptions
[5:0] SEG_0_4x SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[14:8] SEG_1_4x SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[21:16] SEG_2_4x SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data
[29:24] SEG_3_4x SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
LCD display data

Definition at line 5505 of file Nano1X2Series.h.

◆ RESERVE0

uint32_t LCD_T::RESERVE0[1]

Definition at line 5506 of file Nano1X2Series.h.


The documentation for this struct was generated from the following file: