34 #define FREQ_32MHZ 32000000 35 #define FREQ_16MHZ 16000000 38 #define CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001) 39 #define CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002) 40 #define CLK_PWRCTL_HIRC_EN ((uint32_t)0x00000004) 41 #define CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008) 42 #define CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010) 43 #define CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020) 44 #define CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040) 45 #define CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100) 47 #define CLK_PWRCTL_HXT_GAIN_8M ((uint32_t)0x00000000) 48 #define CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000400) 49 #define CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000800) 50 #define CLK_PWRCTL_HXT_GAIN_16M ((uint32_t)0x00000C00) 55 #define CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001) 56 #define CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002) 57 #define CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004) 58 #define CLK_AHBCLK_EBI_EN ((uint32_t)0x00000008) 59 #define CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010) 60 #define CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020) 63 #define CLK_APBCLK_WDT_EN ((uint32_t)0x00000001) 64 #define CLK_APBCLK_RTC_EN ((uint32_t)0x00000002) 65 #define CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004) 66 #define CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008) 67 #define CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010) 68 #define CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020) 69 #define CLK_APBCLK_FDIV_EN ((uint32_t)0x00000040) 70 #define CLK_APBCLK_SC2_EN ((uint32_t)0x00000080) 71 #define CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100) 72 #define CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200) 73 #define CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000) 74 #define CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000) 75 #define CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000) 76 #define CLK_APBCLK_UART0_EN ((uint32_t)0x00010000) 77 #define CLK_APBCLK_UART1_EN ((uint32_t)0x00020000) 78 #define CLK_APBCLK_PWM0_CH01_EN ((uint32_t)0x00100000) 79 #define CLK_APBCLK_PWM0_CH23_EN ((uint32_t)0x00200000) 80 #define CLK_APBCLK_DAC_EN ((uint32_t)0x02000000) 81 #define CLK_APBCLK_LCD_EN ((uint32_t)0x04000000) 82 #define CLK_APBCLK_USBD_EN ((uint32_t)0x08000000) 83 #define CLK_APBCLK_ADC_EN ((uint32_t)0x10000000) 84 #define CLK_APBCLK_I2S_EN ((uint32_t)0x20000000) 85 #define CLK_APBCLK_SC0_EN ((uint32_t)0x40000000) 86 #define CLK_APBCLK_SC1_EN ((uint32_t)0x80000000) 89 #define CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001) 90 #define CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002) 91 #define CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004) 92 #define CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008) 93 #define CLK_CLKSTATUS_HIRC_STB ((uint32_t)0x00000010) 94 #define CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080) 97 #define CLK_PLLCTL_PD ((uint32_t)0x00010000) 98 #define CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000)) 99 #define CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000)) 101 #define CLK_PLL_SRC_N(x) (((x)-1)<<8) 102 #define CLK_PLL_MLP(x) ((x)<<0) 103 #if (__HXT == 12000000) 104 #define CLK_PLLCTL_32MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32)) 105 #define CLK_PLLCTL_28MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28)) 106 #define CLK_PLLCTL_24MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24)) 107 #define CLK_PLLCTL_22MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22)) 108 #define CLK_PLLCTL_16MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16)) 110 # error "The PLL pre-definitions are only valid when external crystal is 12MHz" 112 #define CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32)) 113 #define CLK_PLLCTL_28MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28)) 114 #define CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24)) 115 #define CLK_PLLCTL_22MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22)) 116 #define CLK_PLLCTL_16MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16)) 122 #define CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) 123 #define CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) 124 #define CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) 125 #define CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) 126 #define CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) 129 #define CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) 130 #define CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) 131 #define CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) 132 #define CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) 133 #define CLK_CLKSEL1_ADC_S_HCLK (0x4UL<<CLK_CLKSEL1_ADC_S_Pos) 135 #define CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) 137 #define CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) 138 #define CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) 139 #define CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) 140 #define CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) 141 #define CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) 142 #define CLK_CLKSEL1_TMR1_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR1_S_Pos) 144 #define CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) 145 #define CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) 146 #define CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) 147 #define CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) 148 #define CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) 149 #define CLK_CLKSEL1_TMR0_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR0_S_Pos) 151 #define CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 152 #define CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 153 #define CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 154 #define CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 156 #define CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 157 #define CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 158 #define CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 159 #define CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 161 #define CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) 162 #define CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) 163 #define CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) 164 #define CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) 167 #define CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) 168 #define CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) 170 #define CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) 171 #define CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) 173 #define CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) 174 #define CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) 175 #define CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) 176 #define CLK_CLKSEL2_SC_S_HCLK (0x3UL<<CLK_CLKSEL2_SC_S_Pos) 178 #define CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) 179 #define CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) 180 #define CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) 181 #define CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) 182 #define CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) 183 #define CLK_CLKSEL2_TMR2_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR2_S_Pos) 185 #define CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) 186 #define CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) 187 #define CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) 188 #define CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) 189 #define CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) 190 #define CLK_CLKSEL2_TMR3_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR3_S_Pos) 193 #define CLK_CLKSEL2_FRQDIV0_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) 194 #define CLK_CLKSEL2_FRQDIV0_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) 195 #define CLK_CLKSEL2_FRQDIV0_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) 196 #define CLK_CLKSEL2_FRQDIV0_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV0_S_Pos) 198 #define CLK_CLKSEL2_FRQDIV_S_HXT CLK_CLKSEL2_FRQDIV0_S_HXT 199 #define CLK_CLKSEL2_FRQDIV_S_LXT CLK_CLKSEL2_FRQDIV0_S_LXT 200 #define CLK_CLKSEL2_FRQDIV_S_HCLK CLK_CLKSEL2_FRQDIV0_S_HCLK 201 #define CLK_CLKSEL2_FRQDIV_S_HIRC CLK_CLKSEL2_FRQDIV0_S_HIRC 203 #define CLK_CLKSEL2_FRQDIV1_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) 204 #define CLK_CLKSEL2_FRQDIV1_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) 205 #define CLK_CLKSEL2_FRQDIV1_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) 206 #define CLK_CLKSEL2_FRQDIV1_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV1_S_Pos) 209 #define CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) 210 #define CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) 211 #define CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) 212 #define CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) 215 #define CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) 216 #define CLK_TMR3_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR3_N_Pos) & CLK_CLKDIV1_TMR3_N_Msk) 217 #define CLK_TMR2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR2_N_Pos) & CLK_CLKDIV1_TMR2_N_Msk) 218 #define CLK_TMR1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR1_N_Pos) & CLK_CLKDIV1_TMR1_N_Msk) 219 #define CLK_TMR0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR0_N_Pos) & CLK_CLKDIV1_TMR0_N_Msk) 222 #define CLK_CLKSEL0_STCLKSEL_HCLK (1) 223 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) 226 #define CLK_FRQDIV_EN ((uint32_t)0x00000010) 229 #define CLK_WK_INTSTS_IS ((uint32_t)0x00000001) 235 #define MODULE_APBCLK(x) ((x >>31) & 0x1) 236 #define MODULE_CLKSEL(x) ((x >>29) & 0x3) 237 #define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) 238 #define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) 239 #define MODULE_CLKDIV(x) ((x >>18) & 0x3) 240 #define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) 241 #define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) 242 #define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) 243 #define MODULE_NoMsk 0x0 244 #define NA MODULE_NoMsk 246 #define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) 247 #define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) 248 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) 249 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) 250 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) 251 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) 252 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) 253 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) 257 #define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) 258 #define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) 259 #define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) 260 #define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) 261 #define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) 262 #define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) 264 #define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) 265 #define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) 266 #define ADC_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(19<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) 267 #define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) 268 #define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) 269 #define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) 270 #define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) 271 #define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) 272 #define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) 273 #define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) 274 #define ACMP_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_ACMP_EN_Pos ) 275 #define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) 276 #define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) 277 #define FDIV1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV1_EN_Pos ) 278 #define FDIV0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV0_EN_Pos ) 279 #define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) 280 #define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) 281 #define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) 282 #define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) 283 #define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) 284 #define WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) 286 #define FDIV_MODULE FDIV0_MODULE 297 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
298 void CLK_EnableCKO0(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
299 void CLK_EnableCKO1(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
310 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
311 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
317 uint32_t
CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
void CLK_Idle(void)
This function let system enter to Idle mode.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
void CLK_DisableCKO(void)
This function disable frequency output function.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
void CLK_EnableCKO1(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableCKO1(void)
This function disable frequency output function(1).
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz.
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
void CLK_DisableCKO0(void)
This function disable frequency output function.
void CLK_DisablePLL(void)
This function disable PLL.
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
void CLK_EnableCKO0(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableSysTick(void)
Disable System Tick counter.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
uint32_t CLK_GetPCLKFreq(void)
This function get PCLK frequency. The frequency unit is Hz.