Bits | Field | Descriptions |
[0] | TMR_EN | Timer Counter Enable Control |
| | 0 = Stops/Suspends counting. |
| | 1 = Starts counting. |
| | Note1: Set TMR_EN to 1 enables 24-bit counter keeps up counting from the last stop counting value. |
| | Note2: This bit is auto-cleared by hardware in one-shot mode (MODE_SEL (TMRx_CTL[5:4]) = 00) once the value of 24-bit up counter equals the TMRx_CMPR. |
[1] | SW_RST | Software Reset |
| | Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL [0]) to 0. |
| | 0 = No effect. |
| | 1 = Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_EN (TMRx_CTL [0]) bit. |
| | Note: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles. |
[2] | WAKE_EN | Wake-Up Enable Control |
| | When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU. |
| | 0 = Wake-up trigger event Disabled. |
| | 1 = Wake-up trigger event Enabled. |
[3] | DBGACK_EN | ICE Debug Mode Acknowledge Ineffective Enable Control |
| | 0 = ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged. |
| | 1 = ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not. |
[5:4] | MODE_SEL | Timer Operating Mode Select |
| | 00 = The timer is operating in the one-shot mode. |
| | In this mode, the associated interrupt signal is generated (if TMR_IER [TMR_IE] is enabled) once the value of 24-bit up counter equals the TMRx_CMPR. |
| | And TMR_CTL [TMR_EN] is automatically cleared by hardware. |
| | 01 = The timer is operating in the periodic mode. |
| | In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR. |
| | After that, the 24-bit counter will be reset and starts counting from zero again. |
| | 10 = The timer is operating in the periodic mode with output toggling. |
| | In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR. |
| | After that, the 24-bit counter will be reset and starts counting from zero again. |
| | At the same time, timer controller will also toggle the output pin TMRx_TOG_OUT to its inverse level (from low to high or from high to low). |
| | Note: The default level of TMRx_TOG_OUT after reset is low. |
| | 11 = The timer is operating in continuous counting mode. |
| | In this mode, the associated interrupt signal is generated when TMR_DR = TMR_CMPR (if TMR_IER [TMR_IE] is enabled). |
| | However, the 24-bit up-counter counts continuously without reset. |
[6] | ACMP_EN_TMR | ACMP Trigger Timer Enable Control |
| | This bit high enables the functionality that when ACMP0 is in sigma-delta mode, it could enable Timer. |
| | 0 = ACMP0 trigger timer functionality disabled. |
| | 1 = ACMP0 trigger timer functionality enabled. |
[7] | TMR_ACT | Timer Active Status Bit (Read Only) |
| | This bit indicates the timer counter status of timer. |
| | 0 = Timer is not active. |
| | 1 = Timer is in active. |
[8] | ADC_TEEN | Timer Trigger ADC Enable Control |
| | This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC. |
| | When ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller. |
| | When ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller. |
| | 0 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Disabled. |
| | 1 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Enabled. |
[10] | PDMA_TEEN | Timer Trigger PDMA Enable Control |
| | This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA. |
| | When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller. |
| | When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller. |
| | 0 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Disabled. |
| | 1 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Enabled. |
[11] | CAP_TRG_EN | TCAP_IS Trigger Mode Enable |
| | This bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set. |
| | If this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set. |
| | If this bit is set high and TCAP_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set. |
| | 0 = TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and ADC. |
| | 1 = TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC. |
[12] | EVENT_EN | Event Counting Mode Enable Control |
| | When EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin. |
| | While the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1. |
| | Or, the 24-bit up-counting timer will keep its value unchanged. |
| | 0 = Timer counting is not controlled by external event pin. |
| | 1 = Timer counting is controlled by external event pin. |
[13] | EVENT_EDGE | Event Counting Mode Edge Selection |
| | This bit indicates which edge of external event pin enabling the timer to increase 1. |
| | 0 = A falling edge of external event enabling the timer to increase 1. |
| | 1 = A rising edge of external event enabling the timer to increase 1. |
[14] | EVNT_DEB_EN | External Event De-Bounce Enable Control |
| | When EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal. |
| | In de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK. |
| | 0 = De-bounce circuit Disabled. |
| | 1 = De-bounce circuit Enabled. |
| | Note: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended. |
| | And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption. |
[16] | TCAP_EN | TC Pin Functional Enable Control |
| | This bit controls if the transition on TC pin could be used as timer counter reset function or timer capture function. |
| | 0 = The transition on TC pin is ignored. |
| | 1 = The transition on TC pin will result in the capture or reset of 24-bit timer counter. |
| | Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TC pin transition is ignored (where x = 0 or 2). |
| | Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high (where x = 0 or 2). |
[17] | TCAP_MODE | TC Pin Function Mode Selection |
| | This bit indicates if the transition on TC pin is used as timer counter reset function or timer capture function. |
| | 0 = The transition on TC pin is used as timer capture function. |
| | 1 = The transition on TC pin is used as timer counter reset function. |
| | Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_MODE will be forced to low (where x = 0 or 2). |
[19:18] | TCAP_EDGE | TC Pin Edge Detect Selection |
| | This field defines that active transition of Tcapture pin is for timer counter reset function or for timer capture function. |
| | For timer counter reset function and free-counting mode of timer capture function, the configurations are: |
| | 00 = A falling edge (1 to 0 transition) on Tcapture pin is an active transition. |
| | 01 = A rising edge (0 to 1 transition) on Tcapture pin is an active transition. |
| | 10 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions. |
| | 11 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions. |
| | For trigger-counting mode of timer capture function, the configurations are: |
| | 00 = 1st falling edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting. |
| | 01 = 1st rising edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting. |
| | 10 = Falling edge on Tcapture pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting. |
| | 11 = Rising edge on Tcapture pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting. |
| | Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EDGE will be forced to 11. |
[20] | TCAP_CNT_MOD | Timer Capture Counting Mode Selection |
| | This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high. |
| | If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field. |
| | When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of TC pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. |
| | If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0. |
| | When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. |
| | And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. |
| | And its value will be saved into register TMRx_TCAP. |
| | 0 = Capture with free-counting timer mode. |
| | 1 = Capture with trigger-counting timer mode. |
| | Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_CNT_MOD will be forced to high, the capture with Trigger-counting Timer mode (where x = 0 or 2). |
[22] | TCAP_DEB_EN | TC Pin De-Bounce Enable Control |
| | When CAP_DEB_EN (TMRx_CTL[22]) is set, the TC pin de-bounce circuit will be enabled to eliminate the bouncing of the signal. |
| | In de-bounce circuit the TC pin signal will be sampled 4 times by TMRx_CLK. |
| | 0 = De-bounce circuit Disabled. |
| | 1 = De-bounce circuit Enabled. |
| | Note: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended. |
| | And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption. |
| | Note: When CAP_SRC (TMRx_ECTL[16]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low. |
| | Note: For Timer 1 and 3, when INTR_TRG_EN (TMRx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low. |
[24] | INTR_TRG_EN | Inter-Timer Trigger Function Enable Control |
| | This bit controls if Inter-timer Trigger function is enabled. |
| | If Inter-timer Trigger function is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. |
| | In addition, TMRx+1 will be in trigger-counting mode of capture function. |
| | 0 = Inter-timer trigger function Disabled. |
| | 1 = Inter-timer trigger function Enabled. |
| | Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 0. |
[25] | INTR_TRG_MODE | Inter-Timer Trigger Mode Selection |
| | This bit controls the timer operation mode when inter-timer trigger function is enabled. |
| | When this bit is low, the TMRx will be in counter mode and counting with external Clock Source or event. |
| | In addition, TMRx+1 will be in trigger-counting mode of capture function. |
| | In this mode, TMRx_CMPR control when inter-timer trigger function terminated. |
| | When this bit is high, the TMRx will be in counter mode and counting with external Clock Source or event. |
| | In addition, TMRx+1 will be in trigger-counting mode of capture function. |
| | In this mode, TMRx+1_CMPR control when inter-timer trigger function terminated. |
| | In this mode, TMRx would ignore some incoming event based on the EVNT_DROP_CNT (TMRx_ECTL[31:24]). |
| | And once the TMRx+1 counter value equal or large than TMRx+1_CMPR, TMRx would terminate the operation when next incoming event received. |
| | 0 = Inter-Timer Trigger function wouldn't ignore any incoming event. |
| | 1 = Inter-Timer Trigger function would ignore incoming event based on the EVNT_DROP_CNT (TMRx_ECTL[31:24]). |
| | Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 0. |