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Nano102_112 Series BSP
V3.03.002
The Board Support Package for Nano102_112 Series
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Macros | |
#define | FLASH_BASE ((uint32_t)0x00000000) |
Flash base address. More... | |
#define | SRAM_BASE ((uint32_t)0x20000000) |
SRAM base address. More... | |
#define | APB1PERIPH_BASE ((uint32_t)0x40000000) |
APB1 base address. More... | |
#define | APB2PERIPH_BASE ((uint32_t)0x40100000) |
APB2 base address. More... | |
#define | AHBPERIPH_BASE ((uint32_t)0x50000000) |
AHB base address. More... | |
#define | WDT_BASE (APB1PERIPH_BASE + 0x04000) |
WDT register base address. More... | |
#define | WWDT_BASE (APB1PERIPH_BASE + 0x04100) |
WWDT register base address. More... | |
#define | RTC_BASE (APB1PERIPH_BASE + 0x08000) |
RTC register base address. More... | |
#define | TIMER0_BASE (APB1PERIPH_BASE + 0x10000) |
TIMER0 register base address. More... | |
#define | TIMER1_BASE (APB1PERIPH_BASE + 0x10100) |
TIMER1 register base address. More... | |
#define | I2C0_BASE (APB1PERIPH_BASE + 0x20000) |
I2C0 register base address. More... | |
#define | SPI0_BASE (APB1PERIPH_BASE + 0x30000) |
SPI0 register base address. More... | |
#define | PWM0_BASE (APB1PERIPH_BASE + 0x40000) |
PWM0 register base address. More... | |
#define | UART0_BASE (APB1PERIPH_BASE + 0x50000) |
UART0 register base address. More... | |
#define | LCD_BASE (APB1PERIPH_BASE + 0xB0000) |
LCD register base address. More... | |
#define | ADC_BASE (APB1PERIPH_BASE + 0xE0000) |
ADC register base address. More... | |
#define | TIMER2_BASE (APB2PERIPH_BASE + 0x10000) |
TIMER2 register base address. More... | |
#define | TIMER3_BASE (APB2PERIPH_BASE + 0x10100) |
TIMER3 register base address. More... | |
#define | I2C1_BASE (APB2PERIPH_BASE + 0x20000) |
I2C1 register base address. More... | |
#define | SPI1_BASE (APB2PERIPH_BASE + 0x30000) |
SPI1 register base address. More... | |
#define | UART1_BASE (APB2PERIPH_BASE + 0x50000) |
UART1 register base address. More... | |
#define | SC0_BASE (APB2PERIPH_BASE + 0x90000) |
SC0 register base address. More... | |
#define | SC1_BASE (APB2PERIPH_BASE + 0xB0000) |
SC1 register base address. More... | |
#define | ACMP_BASE (APB2PERIPH_BASE + 0xD0000) |
ACMP register base address. More... | |
#define | SYS_BASE (AHBPERIPH_BASE + 0x00000) |
SYS register base address. More... | |
#define | CLK_BASE (AHBPERIPH_BASE + 0x00200) |
CLK register base address. More... | |
#define | INTID_BASE (AHBPERIPH_BASE + 0x00300) |
INT register base address. More... | |
#define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
GPIO port A register base address. More... | |
#define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
GPIO port B register base address. More... | |
#define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
GPIO port C register base address. More... | |
#define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
GPIO port D register base address. More... | |
#define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
GPIO port E register base address. More... | |
#define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
GPIO port F register base address. More... | |
#define | GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) |
GPIO debounce register base address. More... | |
#define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) |
GPIO bit access register base address. More... | |
#define | PDMA0_BASE (AHBPERIPH_BASE + 0x08000) |
PDMA0 register base address. More... | |
#define | PDMA1_BASE (AHBPERIPH_BASE + 0x08100) |
PDMA1 register base address. More... | |
#define | PDMA2_BASE (AHBPERIPH_BASE + 0x08200) |
PDMA2 register base address. More... | |
#define | PDMA3_BASE (AHBPERIPH_BASE + 0x08300) |
PDMA3 register base address. More... | |
#define | PDMA4_BASE (AHBPERIPH_BASE + 0x08400) |
PDMA4 register base address. More... | |
#define | PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00) |
PDMA global control register base address. More... | |
#define | PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) |
PDMA CRC register base address. More... | |
#define | FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
FMC register base address. More... | |
Memory Mapped Structure for NANO102/112 Series Peripheral
#define ACMP_BASE (APB2PERIPH_BASE + 0xD0000) |
ACMP register base address.
Definition at line 10601 of file Nano1X2Series.h.
#define ADC_BASE (APB1PERIPH_BASE + 0xE0000) |
ADC register base address.
Definition at line 10592 of file Nano1X2Series.h.
#define AHBPERIPH_BASE ((uint32_t)0x50000000) |
#define APB1PERIPH_BASE ((uint32_t)0x40000000) |
APB1 base address.
Definition at line 10576 of file Nano1X2Series.h.
#define APB2PERIPH_BASE ((uint32_t)0x40100000) |
APB2 base address.
Definition at line 10577 of file Nano1X2Series.h.
#define CLK_BASE (AHBPERIPH_BASE + 0x00200) |
CLK register base address.
Definition at line 10604 of file Nano1X2Series.h.
#define FLASH_BASE ((uint32_t)0x00000000) |
Flash base address.
<Peripheral and SRAM base address
Definition at line 10574 of file Nano1X2Series.h.
#define FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
FMC register base address.
Definition at line 10621 of file Nano1X2Series.h.
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) |
GPIO bit access register base address.
Definition at line 10613 of file Nano1X2Series.h.
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
GPIO port A register base address.
Definition at line 10606 of file Nano1X2Series.h.
#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
GPIO port B register base address.
Definition at line 10607 of file Nano1X2Series.h.
#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
GPIO port C register base address.
Definition at line 10608 of file Nano1X2Series.h.
#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
GPIO port D register base address.
Definition at line 10609 of file Nano1X2Series.h.
#define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) |
GPIO debounce register base address.
Definition at line 10612 of file Nano1X2Series.h.
#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
GPIO port E register base address.
Definition at line 10610 of file Nano1X2Series.h.
#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
GPIO port F register base address.
Definition at line 10611 of file Nano1X2Series.h.
#define I2C0_BASE (APB1PERIPH_BASE + 0x20000) |
I2C0 register base address.
Definition at line 10587 of file Nano1X2Series.h.
#define I2C1_BASE (APB2PERIPH_BASE + 0x20000) |
I2C1 register base address.
Definition at line 10596 of file Nano1X2Series.h.
#define INTID_BASE (AHBPERIPH_BASE + 0x00300) |
INT register base address.
Definition at line 10605 of file Nano1X2Series.h.
#define LCD_BASE (APB1PERIPH_BASE + 0xB0000) |
LCD register base address.
Definition at line 10591 of file Nano1X2Series.h.
#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000) |
PDMA0 register base address.
Definition at line 10614 of file Nano1X2Series.h.
#define PDMA1_BASE (AHBPERIPH_BASE + 0x08100) |
PDMA1 register base address.
Definition at line 10615 of file Nano1X2Series.h.
#define PDMA2_BASE (AHBPERIPH_BASE + 0x08200) |
PDMA2 register base address.
Definition at line 10616 of file Nano1X2Series.h.
#define PDMA3_BASE (AHBPERIPH_BASE + 0x08300) |
PDMA3 register base address.
Definition at line 10617 of file Nano1X2Series.h.
#define PDMA4_BASE (AHBPERIPH_BASE + 0x08400) |
PDMA4 register base address.
Definition at line 10618 of file Nano1X2Series.h.
#define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00) |
PDMA global control register base address.
Definition at line 10619 of file Nano1X2Series.h.
#define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) |
PDMA CRC register base address.
Definition at line 10620 of file Nano1X2Series.h.
#define PWM0_BASE (APB1PERIPH_BASE + 0x40000) |
PWM0 register base address.
Definition at line 10589 of file Nano1X2Series.h.
#define RTC_BASE (APB1PERIPH_BASE + 0x08000) |
RTC register base address.
Definition at line 10584 of file Nano1X2Series.h.
#define SC0_BASE (APB2PERIPH_BASE + 0x90000) |
SC0 register base address.
Definition at line 10599 of file Nano1X2Series.h.
#define SC1_BASE (APB2PERIPH_BASE + 0xB0000) |
SC1 register base address.
Definition at line 10600 of file Nano1X2Series.h.
#define SPI0_BASE (APB1PERIPH_BASE + 0x30000) |
SPI0 register base address.
Definition at line 10588 of file Nano1X2Series.h.
#define SPI1_BASE (APB2PERIPH_BASE + 0x30000) |
SPI1 register base address.
Definition at line 10597 of file Nano1X2Series.h.
#define SRAM_BASE ((uint32_t)0x20000000) |
SRAM base address.
Definition at line 10575 of file Nano1X2Series.h.
#define SYS_BASE (AHBPERIPH_BASE + 0x00000) |
SYS register base address.
Definition at line 10603 of file Nano1X2Series.h.
#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000) |
TIMER0 register base address.
Definition at line 10585 of file Nano1X2Series.h.
#define TIMER1_BASE (APB1PERIPH_BASE + 0x10100) |
TIMER1 register base address.
Definition at line 10586 of file Nano1X2Series.h.
#define TIMER2_BASE (APB2PERIPH_BASE + 0x10000) |
TIMER2 register base address.
Definition at line 10594 of file Nano1X2Series.h.
#define TIMER3_BASE (APB2PERIPH_BASE + 0x10100) |
TIMER3 register base address.
Definition at line 10595 of file Nano1X2Series.h.
#define UART0_BASE (APB1PERIPH_BASE + 0x50000) |
UART0 register base address.
Definition at line 10590 of file Nano1X2Series.h.
#define UART1_BASE (APB2PERIPH_BASE + 0x50000) |
UART1 register base address.
Definition at line 10598 of file Nano1X2Series.h.
#define WDT_BASE (APB1PERIPH_BASE + 0x04000) |
WDT register base address.
Definition at line 10582 of file Nano1X2Series.h.
#define WWDT_BASE (APB1PERIPH_BASE + 0x04100) |
WWDT register base address.
Definition at line 10583 of file Nano1X2Series.h.