40 uint32_t u32MasterSlave,
42 uint32_t u32DataWidth,
45 if(u32DataWidth == 32)
62 SYS->IPRST1 &= ~SYS_IPRST1_SPIRST_Msk;
92 spi->
SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
126 if(u32BusClock > u32ClkSrc)
127 u32BusClock = u32ClkSrc;
131 u32Div = (((u32ClkSrc / u32BusClock) + 1) >> 1) - 1;
138 spi->
CLKDIV = (spi->
CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
139 return ( u32ClkSrc / ((u32Div+1)*2) );
165 spi->
CTL &= ~SPI_CTL_FIFOEN_Msk;
187 return ((u32ClkSrc >> 1) / (u32Div + 1));
234 spi->
CTL &= ~SPI_CTL_UNITIEN_Msk;
237 spi->
SLVCTL &= ~SPI_SLVCTL_SLVSTIEN_Msk;
240 spi->
FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
243 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
246 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
249 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
Mini55 series peripheral access layer header file. This file contains all the peripheral register's d...
#define SPI_SSCTL_SSACTPOL_Msk
#define SPI_FIFOCTL_RXOVIEN_Msk
#define SPI_CTL_FIFOEN_Msk
#define SPI_CTL_UNITIEN_Msk
#define SPI_FIFOCTL_RXTH_Pos
#define SPI_FIFOCTL_TXTH_Msk
#define SPI_CTL_DWIDTH_Pos
#define SPI_FIFOCTL_RXRST_Msk
#define SPI_FIFOCTL_TXRST_Msk
#define SPI_CLKDIV_DIVIDER_Msk
#define SPI_FIFOCTL_TXTH_Pos
#define SPI_FIFOCTL_RXTOIEN_Msk
#define SPI_FIFOCTL_RXTHIEN_Msk
#define SPI_FIFOCTL_RXTH_Msk
#define SPI_FIFOCTL_TXTHIEN_Msk
#define SPI_SSCTL_AUTOSS_Msk
#define SYS_IPRST1_SPIRST_Msk
#define SPI_SLVCTL_SLVSTIEN_Msk
#define CLK_CLKSEL1_SPISEL_HXTorLXT
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
#define SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_RXOV_INTEN_MASK
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
#define CLK_CLKSEL1_SPISEL_Msk
#define CLK
Pointer to CLK register structure.
#define SYS
Pointer to SYS register structure.