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Mini51 BSP
V3.02.002
The Board Support Package for Mini51 Series
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#include <Mini51Series.h>
Data Fields | |
__IO uint32_t | ISPCON |
__IO uint32_t | ISPADR |
__IO uint32_t | ISPDAT |
__IO uint32_t | ISPCMD |
__IO uint32_t | ISPTRG |
__I uint32_t | DFBADR |
__I uint32_t | ISPSTA |
@addtogroup FMC Flash Memory Controller(FMC) Memory Mapped Structure for FMC Controller
Definition at line 1635 of file Mini51Series.h.
FMC_T::DFBADR |
Bits | Field | Descriptions |
[31:0] | DFBA | Data Flash Base Address
This register indicates Data Flash start address. It is a read only register. The Data Flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0. |
Definition at line 1883 of file Mini51Series.h.
FMC_T::ISPADR |
Bits | Field | Descriptions |
[31:0] | ISPADR | ISP Address
The NuMicro Mini51TM series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation. |
Definition at line 1879 of file Mini51Series.h.
FMC_T::ISPCMD |
Bits | Field | Descriptions |
[5:0] | ISPCMD | ISP Command
ISP commands are shown below: 0x00 = Read. 0x04 = Read Unique ID. 0x0B = Read Company ID (0xDA). 0x21 = Program. 0x22 = Page Erase. 0x2E = Set Vector Page Re-Map. |
Definition at line 1881 of file Mini51Series.h.
FMC_T::ISPCON |
Bits | Field | Descriptions |
[0] | ISPEN | ISP Enable Control (Write Protect)
Set this bit to enable ISP function. 0 = ISP function Disabled. 1 = ISP function Enabled. |
[1] | BS | Boot Select (Write Protect)
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened. 0 = Boot from APROM. 1 = Boot from LDROM. |
[3] | APUEN | APROM Update Enable Control (Write Protect)
0 = APROM cannot be updated when chip runs in APROM. 1 = APROM can be updated when chip runs in APROM. |
[4] | CFGUEN | CONFIG Update Enable Control (Write Protect)
Writing this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM. 0 = ISP update User Configuration Disabled. 1 = ISP update User Configuration Enabled. |
[5] | LDUEN | LDROM Update Enable Control (Write Protect)
0 = LDROM cannot be updated. 1 = LDROM can be updated when the MCU runs in APROM. |
[6] | ISPFF | ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0 or CBS[0]=1. (2) LDROM writes to itself if LDUEN is set to 0 or CBS[0]=1. (3) User Configuration is erased/programmed when CFGUEN is 0. (4) Destination address is illegal, such as over an available range. Note: Write 1 to clear this bit to 0. |
Definition at line 1878 of file Mini51Series.h.
FMC_T::ISPDAT |
Bits | Field | Descriptions |
[31:0] | ISPDAT | ISP Data
Write data to this register before ISP program operation. Read data from this register after ISP read operation. |
Definition at line 1880 of file Mini51Series.h.
FMC_T::ISPSTA |
Bits | Field | Descriptions |
[0] | ISPGO | ISP Start Trigger (Read Only)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 = ISP operation is finished. 1 = ISP operation is progressed. Note: This bit is the same with ISPTRG bit 0. |
[2:1] | CBS | Config Boot Selection (Read Only)
This is a mirror of CBS in CONFIG0. |
[6] | ISPFF | ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0 or CBS[0]=1. (2) LDROM writes to itself if LDUEN is set to 0 or CBS[0]=1. (3) User Configuration is erased/programmed when CFGUEN is 0. (4) Destination address is illegal, such as over an available range. Write 1 to clear. Note: This bit functions the same as ISPCON bit 6. |
[20:9] | VECMAP | Vector Page Mapping Address (Read Only)
The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}. |
Definition at line 1887 of file Mini51Series.h.
FMC_T::ISPTRG |
Bits | Field | Descriptions |
[0] | ISPGO | ISP Start Trigger (Write Protect)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 = ISP operation is finished. 1 = ISP operation is progressed. |
Definition at line 1882 of file Mini51Series.h.