40 uint32_t u32MasterSlave,
42 uint32_t u32DataWidth,
45 uint32_t u32Pclk, u32Div;
47 if(u32DataWidth == 32)
59 u32Div = (((u32Pclk / u32BusClock) + 1) >> 1) - 1;
67 return ( u32Pclk / ((u32Div+1)*2) );
79 SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI_RST_Msk;
109 spi->
SSR &= ~SPI_SSR_AUTOSS_Msk;
135 if(u32BusClock > u32ClkSrc)
136 u32BusClock = u32ClkSrc;
138 if(u32BusClock != 0 )
140 u32Div = (((u32ClkSrc / u32BusClock) + 1) >> 1) - 1;
147 spi->
DIVIDER = (spi->
DIVIDER & ~SPI_DIVIDER_DIVIDER_Msk) | u32Div;
148 return ( u32ClkSrc / ((u32Div+1)*2) );
174 spi->
CNTRL &= ~SPI_CNTRL_FIFO_Msk;
185 uint32_t u32ApbClock;
189 return ((u32ApbClock >> 1) / (u32Div + 1));
236 spi->
CNTRL &= ~SPI_CNTRL_IE_Msk;
239 spi->
CNTRL2 &= ~SPI_CNTRL2_SSTA_INTEN_Msk;
242 spi->
FIFO_CTL &= ~SPI_FIFO_CTL_TX_INTEN_Msk;
245 spi->
FIFO_CTL &= ~SPI_FIFO_CTL_RX_INTEN_Msk;
248 spi->
FIFO_CTL &= ~SPI_FIFO_CTL_RXOV_INTEN_Msk;
251 spi->
FIFO_CTL &= ~SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;
Mini51 series peripheral access layer header file. This file contains all the peripheral register's d...
#define SPI_FIFO_CTL_RX_THRESHOLD_Pos
#define SPI_CNTRL_FIFO_Msk
#define SPI_FIFO_CTL_TX_THRESHOLD_Msk
#define SPI_FIFO_CTL_RXOV_INTEN_Msk
#define SPI_FIFO_CTL_TX_THRESHOLD_Pos
#define SPI_SSR_SS_LTRIG_Msk
#define SPI_FIFO_CTL_TX_INTEN_Msk
#define SPI_SSR_AUTOSS_Msk
#define SPI_FIFO_CTL_TX_CLR_Msk
#define SPI_CNTRL2_SSTA_INTEN_Msk
#define SPI_CNTRL_TX_BIT_LEN_Pos
#define SPI_DIVIDER_DIVIDER_Msk
#define SYS_IPRSTC2_SPI_RST_Msk
#define SPI_FIFO_CTL_TIMEOUT_INTEN_Msk
#define SPI_SSR_SS_LVL_Msk
#define SPI_FIFO_CTL_RX_INTEN_Msk
#define SPI_FIFO_CTL_RX_CLR_Msk
#define SPI_FIFO_CTL_RX_THRESHOLD_Msk
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
#define SYS
Pointer to SYS register structure.
#define SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_RXOV_INTEN_MASK
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.