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NANO103 BSP V3.01.004
The Board Support Package for Nano103 Series
|
Macros | |
#define | NULL (0) |
NULL pointer. More... | |
#define | TRUE (1) |
Boolean true, define to use in API parameters or return value. More... | |
#define | FALSE (0) |
Boolean false, define to use in API parameters or return value. More... | |
#define | ENABLE (1) |
Enable, define to use in API parameters. More... | |
#define | DISABLE (0) |
Disable, define to use in API parameters. More... | |
#define | BIT0 (0x00000001) |
Bit 0 mask of an 32 bit integer. More... | |
#define | BIT1 (0x00000002) |
Bit 1 mask of an 32 bit integer. More... | |
#define | BIT2 (0x00000004) |
Bit 2 mask of an 32 bit integer. More... | |
#define | BIT3 (0x00000008) |
Bit 3 mask of an 32 bit integer. More... | |
#define | BIT4 (0x00000010) |
Bit 4 mask of an 32 bit integer. More... | |
#define | BIT5 (0x00000020) |
Bit 5 mask of an 32 bit integer. More... | |
#define | BIT6 (0x00000040) |
Bit 6 mask of an 32 bit integer. More... | |
#define | BIT7 (0x00000080) |
Bit 7 mask of an 32 bit integer. More... | |
#define | BIT8 (0x00000100) |
Bit 8 mask of an 32 bit integer. More... | |
#define | BIT9 (0x00000200) |
Bit 9 mask of an 32 bit integer. More... | |
#define | BIT10 (0x00000400) |
Bit 10 mask of an 32 bit integer. More... | |
#define | BIT11 (0x00000800) |
Bit 11 mask of an 32 bit integer. More... | |
#define | BIT12 (0x00001000) |
Bit 12 mask of an 32 bit integer. More... | |
#define | BIT13 (0x00002000) |
Bit 13 mask of an 32 bit integer. More... | |
#define | BIT14 (0x00004000) |
Bit 14 mask of an 32 bit integer. More... | |
#define | BIT15 (0x00008000) |
Bit 15 mask of an 32 bit integer. More... | |
#define | BIT16 (0x00010000) |
Bit 16 mask of an 32 bit integer. More... | |
#define | BIT17 (0x00020000) |
Bit 17 mask of an 32 bit integer. More... | |
#define | BIT18 (0x00040000) |
Bit 18 mask of an 32 bit integer. More... | |
#define | BIT19 (0x00080000) |
Bit 19 mask of an 32 bit integer. More... | |
#define | BIT20 (0x00100000) |
Bit 20 mask of an 32 bit integer. More... | |
#define | BIT21 (0x00200000) |
Bit 21 mask of an 32 bit integer. More... | |
#define | BIT22 (0x00400000) |
Bit 22 mask of an 32 bit integer. More... | |
#define | BIT23 (0x00800000) |
Bit 23 mask of an 32 bit integer. More... | |
#define | BIT24 (0x01000000) |
Bit 24 mask of an 32 bit integer. More... | |
#define | BIT25 (0x02000000) |
Bit 25 mask of an 32 bit integer. More... | |
#define | BIT26 (0x04000000) |
Bit 26 mask of an 32 bit integer. More... | |
#define | BIT27 (0x08000000) |
Bit 27 mask of an 32 bit integer. More... | |
#define | BIT28 (0x10000000) |
Bit 28 mask of an 32 bit integer. More... | |
#define | BIT29 (0x20000000) |
Bit 29 mask of an 32 bit integer. More... | |
#define | BIT30 (0x40000000) |
Bit 30 mask of an 32 bit integer. More... | |
#define | BIT31 (0x80000000) |
Bit 31 mask of an 32 bit integer. More... | |
#define | BYTE0_Msk (0x000000FF) |
Mask to get bit0~bit7 from a 32 bit integer. More... | |
#define | BYTE1_Msk (0x0000FF00) |
Mask to get bit8~bit15 from a 32 bit integer. More... | |
#define | BYTE2_Msk (0x00FF0000) |
Mask to get bit16~bit23 from a 32 bit integer. More... | |
#define | BYTE3_Msk (0xFF000000) |
Mask to get bit24~bit31 from a 32 bit integer. More... | |
#define | GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) |
#define | GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) |
#define | GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) |
#define | GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) |
Variables | |
__I uint32_t | INT_T::IRQ0_SRC |
__I uint32_t | INT_T::IRQ1_SRC |
__I uint32_t | INT_T::IRQ2_SRC |
__I uint32_t | INT_T::IRQ3_SRC |
__I uint32_t | INT_T::IRQ4_SRC |
__I uint32_t | INT_T::IRQ5_SRC |
__I uint32_t | INT_T::IRQ6_SRC |
__I uint32_t | INT_T::IRQ7_SRC |
__I uint32_t | INT_T::IRQ8_SRC |
__I uint32_t | INT_T::IRQ9_SRC |
__I uint32_t | INT_T::IRQ10_SRC |
__I uint32_t | INT_T::IRQ11_SRC |
__I uint32_t | INT_T::IRQ12_SRC |
__I uint32_t | INT_T::IRQ13_SRC |
__I uint32_t | INT_T::IRQ14_SRC |
__I uint32_t | INT_T::IRQ15_SRC |
__I uint32_t | INT_T::IRQ16_SRC |
__I uint32_t | INT_T::IRQ17_SRC |
__I uint32_t | INT_T::IRQ18_SRC |
__I uint32_t | INT_T::IRQ19_SRC |
__I uint32_t | INT_T::IRQ20_SRC |
__I uint32_t | INT_T::IRQ21_SRC |
__I uint32_t | INT_T::IRQ22_SRC |
__I uint32_t | INT_T::IRQ23_SRC |
__I uint32_t | INT_T::IRQ24_SRC |
__I uint32_t | INT_T::IRQ25_SRC |
__I uint32_t | INT_T::IRQ26_SRC |
__I uint32_t | INT_T::IRQ27_SRC |
__I uint32_t | INT_T::IRQ28_SRC |
__I uint32_t | INT_T::IRQ29_SRC |
__I uint32_t | INT_T::IRQ30_SRC |
__I uint32_t | INT_T::IRQ31_SRC |
__IO uint32_t | INT_T::NMI_SEL |
__IO uint32_t | INT_T::MCU_IRQ |
__I uint32_t | SYS_T::PDID |
__IO uint32_t | SYS_T::RSTSTS |
__IO uint32_t | SYS_T::IPRST1 |
__IO uint32_t | SYS_T::IPRST2 |
__IO uint32_t | SYS_T::MISCCTL |
__IO uint32_t | SYS_T::TEMPCTL |
__IO uint32_t | SYS_T::RCCFCTL |
__IO uint32_t | SYS_T::GPA_MFPL |
__IO uint32_t | SYS_T::GPA_MFPH |
__IO uint32_t | SYS_T::GPB_MFPL |
__IO uint32_t | SYS_T::GPB_MFPH |
__IO uint32_t | SYS_T::GPC_MFPL |
__IO uint32_t | SYS_T::GPC_MFPH |
__IO uint32_t | SYS_T::GPD_MFPL |
__IO uint32_t | SYS_T::GPD_MFPH |
__IO uint32_t | SYS_T::GPE_MFPL |
__IO uint32_t | SYS_T::GPF_MFPL |
__IO uint32_t | SYS_T::PORCTL |
__IO uint32_t | SYS_T::BODCTL |
__IO uint32_t | SYS_T::IVREFCTL |
__IO uint32_t | SYS_T::LDOCTL |
__IO uint32_t | SYS_T::BATDIVCTL |
__I uint32_t | SYS_T::WKSTS |
__IO uint32_t | SYS_T::IRC0TCTL |
__IO uint32_t | SYS_T::IRC0TIEN |
__IO uint32_t | SYS_T::IRC0TISTS |
__IO uint32_t | SYS_T::IRC1TCTL |
__IO uint32_t | SYS_T::IRC1TIEN |
__IO uint32_t | SYS_T::IRC1TISTS |
__IO uint32_t | SYS_T::MIRCTCTL |
__IO uint32_t | SYS_T::MIRCTIEN |
__IO uint32_t | SYS_T::MIRCTISTS |
__O uint32_t | SYS_T::REGLCTL |
__IO uint32_t | SYS_T::RPDBCLK |
__IO uint32_t | CLK_T::PWRCTL |
__IO uint32_t | CLK_T::AHBCLK |
__IO uint32_t | CLK_T::APBCLK |
__I uint32_t | CLK_T::STATUS |
__IO uint32_t | CLK_T::CLKSEL0 |
__IO uint32_t | CLK_T::CLKSEL1 |
__IO uint32_t | CLK_T::CLKSEL2 |
__IO uint32_t | CLK_T::CLKDIV0 |
__IO uint32_t | CLK_T::CLKDIV1 |
__IO uint32_t | CLK_T::PLLCTL |
__IO uint32_t | CLK_T::CLKOCTL |
__IO uint32_t | CLK_T::WKINTSTS |
__IO uint32_t | CLK_T::APBDIV |
__IO uint32_t | CLK_T::CLKDCTL |
__IO uint32_t | CLK_T::CLKDIE |
__IO uint32_t | CLK_T::CLKDSTS |
__IO uint32_t | CLK_T::CDUPB |
__IO uint32_t | CLK_T::CDLOWB |
__IO uint32_t | FMC_T::ISPCTL |
__IO uint32_t | FMC_T::ISPADDR |
__IO uint32_t | FMC_T::ISPDAT |
__IO uint32_t | FMC_T::ISPCMD |
__IO uint32_t | FMC_T::ISPTRG |
__I uint32_t | FMC_T::DFBA |
__IO uint32_t | FMC_T::FTCTL |
__IO uint32_t | FMC_T::ISPSTS |
__O uint32_t | FMC_T::KEY0 |
__O uint32_t | FMC_T::KEY1 |
__O uint32_t | FMC_T::KEY2 |
__IO uint32_t | FMC_T::KEYTRG |
__IO uint32_t | FMC_T::KEYSTS |
__I uint32_t | FMC_T::KECNT |
__I uint32_t | FMC_T::KPCNT |
__IO uint32_t | GPIO_T::MODE |
__IO uint32_t | GPIO_T::DINOFF |
__IO uint32_t | GPIO_T::DOUT |
__IO uint32_t | GPIO_T::DATMSK |
__I uint32_t | GPIO_T::PIN |
__IO uint32_t | GPIO_T::DBEN |
__IO uint32_t | GPIO_T::INTTYPE |
__IO uint32_t | GPIO_T::INTEN |
__IO uint32_t | GPIO_T::INTSRC |
__IO uint32_t | GPIO_T::PUEN |
__I uint32_t | GPIO_T::INTSTS |
__IO uint32_t | GP_DB_T::DBCTL |
__IO uint32_t | PDMA_CH_T::CTLn |
__IO uint32_t | PDMA_CH_T::SAn |
__IO uint32_t | PDMA_CH_T::DAn |
__IO uint32_t | PDMA_CH_T::CNTn |
__I uint32_t | PDMA_CH_T::CSAn |
__I uint32_t | PDMA_CH_T::CDAn |
__I uint32_t | PDMA_CH_T::CCNTn |
__IO uint32_t | PDMA_CH_T::INTENn |
__IO uint32_t | PDMA_CH_T::INTSTSn |
__IO uint32_t | PDMA_CH_T::TOCn |
__IO uint32_t | DMA_CRC_T::CTL |
__IO uint32_t | DMA_CRC_T::DMASA |
__IO uint32_t | DMA_CRC_T::DMABCNT |
__I uint32_t | DMA_CRC_T::DMACSA |
__I uint32_t | DMA_CRC_T::DMACBCNT |
__IO uint32_t | DMA_CRC_T::DMAINTEN |
__IO uint32_t | DMA_CRC_T::DMAISTS |
__IO uint32_t | DMA_CRC_T::DAT |
__IO uint32_t | DMA_CRC_T::SEED |
__I uint32_t | DMA_CRC_T::CHECKSUM |
__IO uint32_t | DMA_GCR_T::GCTL |
__IO uint32_t | DMA_GCR_T::REQSEL0 |
__IO uint32_t | DMA_GCR_T::REQSEL1 |
__I uint32_t | DMA_GCR_T::GINTSTS |
__IO uint32_t | TIMER_T::CTL |
__IO uint32_t | TIMER_T::PRECNT |
__IO uint32_t | TIMER_T::CMP |
__IO uint32_t | TIMER_T::INTEN |
__IO uint32_t | TIMER_T::INTSTS |
__IO uint32_t | TIMER_T::CNT |
__I uint32_t | TIMER_T::CAP |
__IO uint32_t | TIMER_T::ECTL |
__IO uint32_t | PWM_T::CTL0 |
__IO uint32_t | PWM_T::CTL1 |
__IO uint32_t | PWM_T::CLKSRC |
__IO uint32_t | PWM_T::CLKPSC0_1 |
__IO uint32_t | PWM_T::CLKPSC2_3 |
__IO uint32_t | PWM_T::CLKPSC4_5 |
__IO uint32_t | PWM_T::CNTEN |
__IO uint32_t | PWM_T::CNTCLR |
__IO uint32_t | PWM_T::PERIOD [6] |
__IO uint32_t | PWM_T::CMPDAT [6] |
__IO uint32_t | PWM_T::DTCTL0_1 |
__IO uint32_t | PWM_T::DTCTL2_3 |
__IO uint32_t | PWM_T::DTCTL4_5 |
__I uint32_t | PWM_T::CNT [6] |
__IO uint32_t | PWM_T::WGCTL0 |
__IO uint32_t | PWM_T::WGCTL1 |
__IO uint32_t | PWM_T::MSKEN |
__IO uint32_t | PWM_T::MSK |
__IO uint32_t | PWM_T::BNF |
__IO uint32_t | PWM_T::FAILBRK |
__IO uint32_t | PWM_T::BRKCTL0_1 |
__IO uint32_t | PWM_T::BRKCTL2_3 |
__IO uint32_t | PWM_T::BRKCTL4_5 |
__IO uint32_t | PWM_T::POLCTL |
__IO uint32_t | PWM_T::POEN |
__O uint32_t | PWM_T::SWBRK |
__IO uint32_t | PWM_T::INTEN0 |
__IO uint32_t | PWM_T::INTEN1 |
__IO uint32_t | PWM_T::INTSTS0 |
__IO uint32_t | PWM_T::INTSTS1 |
__IO uint32_t | PWM_T::ADCTS0 |
__IO uint32_t | PWM_T::ADCTS1 |
__IO uint32_t | PWM_T::STATUS |
__IO uint32_t | PWM_T::CAPINEN |
__IO uint32_t | PWM_T::CAPCTL |
__I uint32_t | PWM_T::CAPSTS |
__I uint32_t | PWM_T::RCAPDAT0 |
__I uint32_t | PWM_T::FCAPDAT0 |
__I uint32_t | PWM_T::RCAPDAT1 |
__I uint32_t | PWM_T::FCAPDAT1 |
__I uint32_t | PWM_T::RCAPDAT2 |
__I uint32_t | PWM_T::FCAPDAT2 |
__I uint32_t | PWM_T::RCAPDAT3 |
__I uint32_t | PWM_T::FCAPDAT3 |
__I uint32_t | PWM_T::RCAPDAT4 |
__I uint32_t | PWM_T::FCAPDAT4 |
__I uint32_t | PWM_T::RCAPDAT5 |
__I uint32_t | PWM_T::FCAPDAT5 |
__IO uint32_t | PWM_T::CAPIEN |
__IO uint32_t | PWM_T::CAPIF |
__IO uint32_t | PWM_T::SELFTEST |
__I uint32_t | PWM_T::PBUF0 |
__I uint32_t | PWM_T::PBUF2 |
__I uint32_t | PWM_T::PBUF4 |
__I uint32_t | PWM_T::CMPBUF0 |
__I uint32_t | PWM_T::CMPBUF1 |
__I uint32_t | PWM_T::CMPBUF2 |
__I uint32_t | PWM_T::CMPBUF3 |
__I uint32_t | PWM_T::CMPBUF4 |
__I uint32_t | PWM_T::CMPBUF5 |
__IO uint32_t | WDT_T::CTL |
__IO uint32_t | WDT_T::INTEN |
__IO uint32_t | WDT_T::STATUS |
__O uint32_t | WWDT_T::RLDCNT |
__IO uint32_t | WWDT_T::CTL |
__IO uint32_t | WWDT_T::INTEN |
__IO uint32_t | WWDT_T::STATUS |
__I uint32_t | WWDT_T::CNT |
__IO uint32_t | RTC_T::INIT |
__IO uint32_t | RTC_T::RWEN |
__IO uint32_t | RTC_T::FREQADJ |
__IO uint32_t | RTC_T::TIME |
__IO uint32_t | RTC_T::CAL |
__IO uint32_t | RTC_T::CLKFMT |
__IO uint32_t | RTC_T::WEEKDAY |
__IO uint32_t | RTC_T::TALM |
__IO uint32_t | RTC_T::CALM |
__I uint32_t | RTC_T::LEAPYEAR |
__IO uint32_t | RTC_T::INTEN |
__IO uint32_t | RTC_T::INTSTS |
__IO uint32_t | RTC_T::TICK |
__IO uint32_t | RTC_T::TAMSK |
__IO uint32_t | RTC_T::CAMSK |
__IO uint32_t | RTC_T::SPRCTL |
__IO uint32_t | RTC_T::SPR [5] |
__IO uint32_t | RTC_T::LXTCTL |
__IO uint32_t | RTC_T::LXTOCTL |
__IO uint32_t | RTC_T::LXTICTL |
__IO uint32_t | RTC_T::TAMPCTL |
__IO uint32_t | RTC_T::MISCCTL |
__IO uint32_t | UART_T::DAT |
__IO uint32_t | UART_T::CTRL |
__IO uint32_t | UART_T::LINE |
__IO uint32_t | UART_T::INTEN |
__IO uint32_t | UART_T::INTSTS |
__IO uint32_t | UART_T::TRSR |
__IO uint32_t | UART_T::FIFOSTS |
__IO uint32_t | UART_T::MODEM |
__IO uint32_t | UART_T::TOUT |
__IO uint32_t | UART_T::BAUD |
__IO uint32_t | UART_T::IRDA |
__IO uint32_t | UART_T::ALTCTL |
__IO uint32_t | UART_T::FUNCSEL |
__IO uint32_t | UART_T::BRCOMPAT |
__IO uint32_t | UART_T::WKUPEN |
__IO uint32_t | UART_T::WKUPSTS |
__IO uint32_t | SC_T::DAT |
__IO uint32_t | SC_T::CTL |
__IO uint32_t | SC_T::ALTCTL |
__IO uint32_t | SC_T::EGT |
__IO uint32_t | SC_T::RXTOUT |
__IO uint32_t | SC_T::ETUCTL |
__IO uint32_t | SC_T::INTEN |
__IO uint32_t | SC_T::INTSTS |
__IO uint32_t | SC_T::STATUS |
__IO uint32_t | SC_T::PINCTL |
__IO uint32_t | SC_T::TMRCTL0 |
__IO uint32_t | SC_T::TMRCTL1 |
__IO uint32_t | SC_T::TMRCTL2 |
__IO uint32_t | SC_T::UARTCTL |
__IO uint32_t | SC_T::ACTCTL |
__IO uint32_t | I2C_T::CTL |
__IO uint32_t | I2C_T::INTSTS |
__I uint32_t | I2C_T::STATUS |
__IO uint32_t | I2C_T::CLKDIV |
__IO uint32_t | I2C_T::TOCTL |
__IO uint32_t | I2C_T::DAT |
__IO uint32_t | I2C_T::ADDR0 |
__IO uint32_t | I2C_T::ADDR1 |
__IO uint32_t | I2C_T::ADDRMSK0 |
__IO uint32_t | I2C_T::ADDRMSK1 |
__IO uint32_t | I2C_T::CTL2 |
__IO uint32_t | I2C_T::STATUS2 |
__IO uint32_t | SPI_T::CTL |
__IO uint32_t | SPI_T::STATUS |
__IO uint32_t | SPI_T::CLKDIV |
__IO uint32_t | SPI_T::SSCTL |
__I uint32_t | SPI_T::RX0 |
__I uint32_t | SPI_T::RX1 |
__O uint32_t | SPI_T::TX0 |
__O uint32_t | SPI_T::TX1 |
__IO uint32_t | SPI_T::PDMACTL |
__IO uint32_t | SPI_T::FIFOCTL |
__I uint32_t | ADC_T::DAT [18] |
__IO uint32_t | ADC_T::CTL |
__IO uint32_t | ADC_T::CHEN |
__IO uint32_t | ADC_T::CMP0 |
__IO uint32_t | ADC_T::CMP1 |
__IO uint32_t | ADC_T::STATUS |
__I uint32_t | ADC_T::PDMA |
__IO uint32_t | ADC_T::PWD |
__IO uint32_t | ADC_T::CALCTL |
__IO uint32_t | ADC_T::CALWORD |
__IO uint32_t | ADC_T::EXTSMPT0 |
__IO uint32_t | ADC_T::EXTSMPT1 |
__IO uint32_t | ACMP_T::CTL0 |
__IO uint32_t | ACMP_T::STATUS |
__IO uint32_t | ACMP_T::VREF |
NANO103 Legacy Constants
#define BIT0 (0x00000001) |
#define BIT1 (0x00000002) |
#define BIT10 (0x00000400) |
#define BIT11 (0x00000800) |
#define BIT12 (0x00001000) |
#define BIT13 (0x00002000) |
#define BIT14 (0x00004000) |
#define BIT15 (0x00008000) |
#define BIT16 (0x00010000) |
#define BIT17 (0x00020000) |
#define BIT18 (0x00040000) |
#define BIT19 (0x00080000) |
#define BIT2 (0x00000004) |
#define BIT20 (0x00100000) |
#define BIT21 (0x00200000) |
#define BIT22 (0x00400000) |
#define BIT23 (0x00800000) |
#define BIT24 (0x01000000) |
#define BIT25 (0x02000000) |
#define BIT26 (0x04000000) |
#define BIT27 (0x08000000) |
#define BIT28 (0x10000000) |
#define BIT29 (0x20000000) |
#define BIT3 (0x00000008) |
#define BIT30 (0x40000000) |
#define BIT31 (0x80000000) |
#define BIT4 (0x00000010) |
#define BIT5 (0x00000020) |
#define BIT6 (0x00000040) |
#define BIT7 (0x00000080) |
#define BIT8 (0x00000100) |
#define BIT9 (0x00000200) |
#define BYTE0_Msk (0x000000FF) |
#define BYTE1_Msk (0x0000FF00) |
#define BYTE2_Msk (0x00FF0000) |
#define BYTE3_Msk (0xFF000000) |
#define DISABLE (0) |
#define ENABLE (1) |
#define FALSE (0) |
#define GET_BYTE0 | ( | u32Param | ) | ((u32Param & BYTE0_Msk) ) |
#define GET_BYTE1 | ( | u32Param | ) | ((u32Param & BYTE1_Msk) >> 8) |
#define GET_BYTE2 | ( | u32Param | ) | ((u32Param & BYTE2_Msk) >> 16) |
#define GET_BYTE3 | ( | u32Param | ) | ((u32Param & BYTE3_Msk) >> 24) |
#define TRUE (1) |
SC_T::ACTCTL |
[0x0040] SC Activation Control Register.
Bits | Field | Descriptions |
---|---|---|
[4:0] | T1EXT | Configurable Cycles T1EXT in Hardware Activation |
This field provide the configurable cycles to extend the Activation time T1 | ||
The cycle scaling factor is 2048. | ||
Extend cycles = (filled value * 2048) cycles. | ||
Refer to SC Activation Sequence in Figure 6.15-4 SC Activation Sequence. | ||
For example, | ||
SCLK = 4Mhz, each cycle = 0.25us,. | ||
Filled 20 to this field | ||
Extend time = 20*2048*0.25us = 10.24 ms. | ||
Note: setting 0 to this field conforms to the protocol ISO/IEC 7816-3 |
PWM_T::ADCTS0 |
[0x00f8] PWM0 Trigger ADC Source Select Register 0
Bits | Field | Descriptions |
---|---|---|
[3:0] | TRGSEL0 | PWM0_CH0 Trigger ADC Source Select |
0000 = PWM0_CH0 zero point. | ||
0001 = PWM0_CH0 period point. | ||
0010 = PWM0_CH0 zero or period point. | ||
0011 = PWM0_CH0 up-count CMPDAT point. | ||
0100 = PWM0_CH0 down-count CMPDAT point. | ||
0101 = Reserved. | ||
0110 = Reserved. | ||
0111 = Reserved. | ||
1000 = PWM0_CH1 up-count CMPDAT point. | ||
1001 = PWM0_CH1 down-count CMPDAT point. | ||
Others reserved | ||
[7] | TRGEN0 | PWM0_CH0 Trigger EADC Enable Bit |
0 = PWM0_CH0 Trigger EADC Disabled. | ||
1 = PWM0_CH0 Trigger EADC Enabled. | ||
[11:8] | TRGSEL1 | PWM0_CH1 Trigger ADC Source Select |
0000 = PWM0_CH0 zero point. | ||
0001 = PWM0_CH0 period point. | ||
0010 = PWM0_CH0 zero or period point. | ||
0011 = PWM0_CH0 up-count CMPDAT point. | ||
0100 = PWM0_CH0 down-count CMPDAT point. | ||
0101 = Reserved. | ||
0110 = Reserved. | ||
0111 = Reserved. | ||
1000 = PWM0_CH1 up-count CMPDAT point. | ||
1001 = PWM0_CH1 down-count CMPDAT point. | ||
Others reserved | ||
[15] | TRGEN1 | PWM0_CH1 Trigger EADC Enable Bit |
0 = PWM0_CH1 Trigger EADC Disabled. | ||
1 = PWM0_CH1 Trigger EADC Enabled. | ||
[19:16] | TRGSEL2 | PWM0_CH2 Trigger ADC Source Select |
0000 = PWM0_CH2 zero point. | ||
0001 = PWM0_CH2 period point. | ||
0010 = PWM0_CH2 zero or period point. | ||
0011 = PWM0_CH2 up-count CMPDAT point. | ||
0100 = PWM0_CH2 down-count CMPDAT point. | ||
0101 = Reserved. | ||
0110 = Reserved. | ||
0111 = Reserved. | ||
1000 = PWM0_CH3 up-count CMPDAT point. | ||
1001 = PWM0_CH3 down-count CMPDAT point. | ||
Others reserved | ||
[23] | TRGEN2 | PWM0_CH2 Trigger EADC Enable Bit |
0 = PWM0_CH2 Trigger EADC Disabled. | ||
1 = PWM0_CH2 Trigger EADC Enabled. | ||
[27:24] | TRGSEL3 | PWM0_CH3 Trigger ADC Source Select |
0000 = PWM0_CH2 zero point. | ||
0001 = PWM0_CH2 period point. | ||
0010 = PWM0_CH2 zero or period point. | ||
0011 = PWM0_CH2 up-count CMPDAT point. | ||
0100 = PWM0_CH2 down-count CMPDAT point. | ||
0101 = Reserved. | ||
0110 = Reserved. | ||
0111 = Reserved. | ||
1000 = PWM0_CH3 up-count CMPDAT point. | ||
1001 = PWM0_CH3 down-count CMPDAT point. | ||
Others reserved | ||
[31] | TRGEN3 | PWM0_CH3 Trigger EADC Enable Bit |
0 = PWM0_CH3 Trigger EADC Disabled. | ||
1 = PWM0_CH3 Trigger EADC Enabled. |
PWM_T::ADCTS1 |
[0x00fc] PWM0 Trigger ADC Source Select Register 1
Bits | Field | Descriptions |
---|---|---|
[3:0] | TRGSEL4 | PWM0_CH4 Trigger ADC Source Select |
0000 = PWM0_CH4 zero point. | ||
0001 = PWM0_CH4 period point. | ||
0010 = PWM0_CH4 zero or period point. | ||
0011 = PWM0_CH4 up-count CMPDAT point. | ||
0100 = PWM0_CH4 down-count CMPDAT point. | ||
0101 = Reserved. | ||
0110 = Reserved. | ||
0111 = Reserved. | ||
1000 = PWM0_CH5 up-count CMPDAT point. | ||
1001 = PWM0_CH5 down-count CMPDAT point. | ||
Others reserved | ||
[7] | TRGEN4 | PWM0_CH4 Trigger EADC Enable Bit |
0 = PWM0_CH4 Trigger EADC Disabled. | ||
1 = PWM0_CH4 Trigger EADC Enabled. | ||
[11:8] | TRGSEL5 | PWM0_CH5 Trigger ADC Source Select |
0000 = PWM0_CH4 zero point. | ||
0001 = PWM0_CH4 period point. | ||
0010 = PWM0_CH4 zero or period point. | ||
0011 = PWM0_CH4 up-count CMPDAT point. | ||
0100 = PWM0_CH4 down-count CMPDAT point. | ||
0101 = Reserved. | ||
0110 = Reserved. | ||
0111 = Reserved. | ||
1000 = PWM0_CH5 up-count CMPDAT point. | ||
1001 = PWM0_CH5 down-count CMPDAT point. | ||
Others reserved | ||
[15] | TRGEN5 | PWM0_CH5 Trigger EADC Enable Bit |
0 = PWM0_CH5 Trigger EADC Disabled. | ||
1 = PWM0_CH5 Trigger EADC Enabled. |
I2C_T::ADDR0 |
[0x0018] I2C Slave Address Register0
Bits | Field | Descriptions |
---|---|---|
[0] | GC | General Call Function Control |
0 = General Call Function Disabled. | ||
1 = General Call Function Enabled. | ||
Note: Refer to Address Register section for more detailed information. | ||
[7:1] | ADDR | I2C Salve Address Bits |
The content of this register is irrelevant when the device is in Master mode | ||
In the Slave mode, the seven most significant bits must be loaded with the device's own address | ||
The device will react if either of the address is matched. |
I2C_T::ADDR1 |
[0x001c] I2C Slave Address Register1
Bits | Field | Descriptions |
---|---|---|
[0] | GC | General Call Function Control |
0 = General Call Function Disabled. | ||
1 = General Call Function Enabled. | ||
Note: Refer to Address Register section for more detailed information. | ||
[7:1] | ADDR | I2C Salve Address Bits |
The content of this register is irrelevant when the device is in Master mode | ||
In the Slave mode, the seven most significant bits must be loaded with the device's own address | ||
The device will react if either of the address is matched. |
I2C_T::ADDRMSK0 |
[0x0028] I2C Slave Address Mask Register0
Bits | Field | Descriptions |
---|---|---|
[7:1] | ADDRMSK | I2C Slave Address Mask Bits |
0 = Mask disable (the received corresponding register bit should be exact the same as address register). | ||
1 = Mask enable (the received corresponding address bit is don't care). | ||
I2C bus controllers support multiple address recognition with two address mask register | ||
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care | ||
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
I2C_T::ADDRMSK1 |
[0x002c] I2C Slave Address Mask Register1
Bits | Field | Descriptions |
---|---|---|
[7:1] | ADDRMSK | I2C Slave Address Mask Bits |
0 = Mask disable (the received corresponding register bit should be exact the same as address register). | ||
1 = Mask enable (the received corresponding address bit is don't care). | ||
I2C bus controllers support multiple address recognition with two address mask register | ||
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care | ||
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
CLK_T::AHBCLK |
[0x0004] AHB Devices Clock Enable Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | GPIOCKEN | GPIO Controller Clock Enable Control |
0 = GPIO peripheral clock Disabled. | ||
1 = GPIO peripheral clock Enabled. | ||
[1] | PDMACKEN | PDMA Controller Clock Enable Bit |
0 = PDMA peripheral clock Disabled. | ||
1 = PDMA peripheral clock Enabled. | ||
[2] | ISPCKEN | Flash ISP Controller Clock Enable Bit |
0 = Flash ISP peripheral clock Disabled. | ||
1 = Flash ISP peripheral clock Enabled. | ||
[4] | SRAMCKEN | SRAM Controller Clock Enable Control Bit |
0 = SRAM peripheral clock Disabled. | ||
1 = SRAM peripheral clock Enabled. | ||
[5] | STCKEN | System Tick Clock Enable Control Bit |
0 = System Tick Clock Disabled. | ||
1 = System Tick Clock Enabled. |
UART_T::ALTCTL |
[0x0034] UART Alternate Control State Register.
Bits | Field | Descriptions |
---|---|---|
[2:0] | BRKFL | LIN TX Break Field Count |
The field contains 3-bit LIN TX break field count. | ||
Note: The break field length is BRKFL + 8. | ||
[5:4] | LINHSEL | LIN Header Selection |
00 = The LIN header includes break field. | ||
01 = The LIN header includes break field + sync field. | ||
10 = The LIN header includes break field + sync field + PID field. | ||
11 = Reserved. | ||
[6] | LINRXEN | LIN RX Enable Control |
When LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (LININT) | ||
0 = LIN RX mode Disabled. | ||
1 = LIN RX mode Enabled. | ||
[7] | LINTXEN | LIN TX Header Trigger Enable Bit |
The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting LINHSEL (UART_ALT_CSR[5:4]). | ||
0 = Send LIN TX header Disabled. | ||
1 = Send LIN TX header Enabled. | ||
Note1: This bit will be cleared automatically and generate a interrupt to CPU (LININT). | ||
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LINHSEL (UART_ALT_CSR[5:4]) field) transfer operation finished, this bit will be cleared automatically. | ||
Note3: If user wants to receive transmit data, it recommended to enable LINRXEN bit. | ||
[8] | BITERREN | Bit Error Detect Enable Bit |
0 = Bit error detection Disabled. | ||
1 = Bit error detection Enabled. | ||
Note: In LIN function mode, when bit error occurs, the BITEF (UART_TRSR[5]) flag will be asserted | ||
If the LINIEN (UART_IER[8]) = 1, an interrupt will be generated . | ||
[16] | RS485NMM | RS-485 Normal Multi-drop Operation Mode (NMM) |
0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. | ||
1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. | ||
Note: It cannot be active with RS-485_AAD operation mode. | ||
[17] | RS485AAD | RS-485 Auto Address Detection Operation Mode (AAD) |
0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. | ||
1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. | ||
Note: It cannot be active with RS485NMM operation mode. | ||
[18] | RS485AUD | RS-485 Auto Direction Function (AUD) |
0 = RS-485 Auto Direction Operation function (AUD) Disabled. | ||
1 = RS-485 Auto Direction Operation function (AUD) Enabled. | ||
Note: It can be active with RS485AAD or RS485NMM operation mode. | ||
[19] | ADDRDEN | RS-485 Address Detection Enable Bit |
This bit is used to enable RS-485 Address Detection mode. | ||
0 = Address detection mode Disabled. | ||
1 = Address detection mode Enabled. | ||
Note: This bit is used for RS-485 any operation mode. | ||
[31:24] | ADRMPID | Address / PID Match Value Register |
When in the RS-485 Function Mode, this field contains the RS-485 address match values. | ||
When in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (PID [5:0]), hardware will calculate P0 and P1. | ||
Note: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). |
SC_T::ALTCTL |
[0x0008] SC Alternate Control Register.
Bits | Field | Descriptions |
---|---|---|
[0] | TXRST | TX Software Reset |
When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. | ||
0 = No effect. | ||
1 = Reset the TX internal state machine and pointers. | ||
Note: This bit will be auto cleared after reset is complete. | ||
[1] | RXRST | Rx Software Reset |
When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared. | ||
0 = No effect. | ||
1 = Reset the Rx internal state machine and pointers. | ||
Note: This bit will be auto cleared after reset is complete. | ||
[2] | DACTEN | Deactivation Sequence Generator Enable Bit |
This bit enables SC controller to initiate the card by deactivation sequence | ||
0 = No effect. | ||
1 = Deactivation sequence generator Enabled. | ||
Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
Note2: This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time. | ||
Note3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
[3] | ACTEN | Activation Sequence Generator Enable Bit |
This bit enables SC controller to initiate the card by activation sequence | ||
0 = No effect. | ||
1 = Activation sequence generator Enabled. | ||
Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0. | ||
Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
[4] | WARSTEN | Warm Reset Sequence Generator Enable Bit |
This bit enables SC controller to initiate the card by warm reset sequence | ||
0 = No effect. | ||
1 = Warm reset sequence generator Enabled. | ||
Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0. | ||
Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time. | ||
Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
[5] | CNTEN0 | Internal Timer0 Start Enable Bit |
This bit enables Timer 0 to start counting | ||
Software can fill 0 to stop it and set 1 to reload and count. | ||
0 = Stops counting. | ||
1 = Start counting. | ||
Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 11,01,10. | ||
Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. | ||
Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
[6] | CNTEN1 | Internal Timer1 Start Enable Bit |
This bit enables Timer 1 to start counting | ||
Software can fill 0 to stop it and set 1 to reload and count. | ||
0 = Stops counting. | ||
1 = Start counting. | ||
Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11 | ||
Do not fill in CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01. | ||
Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. | ||
Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
[7] | CNTEN2 | Internal Timer2 Start Enable Bit |
This bit enables Timer 2 to start counting | ||
Software can fill 0 to stop it and set 1 to reload and count. | ||
0 = Stops counting. | ||
1 = Start counting. | ||
Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11 | ||
Do not fill in CNTEN2 when TMRSEL(SC_CTL[14:13])= 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10. | ||
Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. | ||
Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
[9:8] | INITSEL | Initial Timing Selection |
This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation). | ||
Unit: SC clock | ||
Activation: Refer to SC Activation Sequence in Figure 6.15-4 SC Activation Sequence. | ||
Warm-reset: Refer to Warm-Reset Sequence in Figure 6.15-5 SC Warm Reset Sequence | ||
Deactivation: Refer to Deactivation Sequence in Figure 6.15-6 SC Deactivation Sequence | ||
Note: When set Activation and Warm reset in mode 11, it may have deviation at most 128 cycles. | ||
[12] | RXBGTEN | Receiver Block Guard Time Function Enable Bit |
0 = Receiver block guard time function Disabled. | ||
1 = Receiver block guard time function Enabled. | ||
[13] | ACTSTS0 | Internal Timer0 Active State (Read Only) |
This bit indicates the timer counter status of timer0. | ||
0 = Timer0 is not active. | ||
1 = Timer0 is active. | ||
Note: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0]). | ||
[14] | ACTSTS1 | Internal Timer1 Active State (Read Only) |
This bit indicates the timer counter status of timer1. | ||
0 = Timer1 is not active. | ||
1 = Timer1 is active. | ||
Note: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0]). | ||
[15] | ACTSTS2 | Internal Timer2 Active State (Read Only) |
This bit indicates the timer counter status of timer2. | ||
0 = Timer2 is not active. | ||
1 = Timer2 is active. | ||
Note: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0]). | ||
[16] | OUTSEL | Smartcard Data Pin Output Mode Selection |
Use this bit to select smartcard data pin output mode. | ||
0 = Quasi mode. | ||
1 = Open-drain mode. |
CLK_T::APBCLK |
[0x0008] APB Devices Clock Enable Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | WDTCKEN | Watchdog Timer Clock Enable Control |
This is a protected register. Please refer to open lock sequence to program it. | ||
This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC. | ||
0 = Watchdog Timer Clock Disabled. | ||
1 = Watchdog Timer Clock Enabled. | ||
[1] | RTCCKEN | Real-time-clock Clock Enable Control |
This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT. | ||
0 = Real-time-clock Clock Disabled. | ||
1 = Real-time-clock Clock Enabled. | ||
[2] | TMR0CKEN | Timer0 Clock Enable Control |
0 = Timer0 Clock Disabled. | ||
1 = Timer0 Clock Enabled. | ||
[3] | TMR1CKEN | Timer1 Clock Enable Control |
0 = Timer1 Clock Disabled. | ||
1 = Timer1 Clock Enabled. | ||
[4] | TMR2CKEN | Timer2 Clock Enable Control |
0 = Timer2 Clock Disabled. | ||
1 = Timer2 Clock Enabled. | ||
[5] | TMR3CKEN | Timer3 Clock Enable Control |
0 = Timer3 Clock Disabled. | ||
1 = Timer3 Clock Enabled. | ||
[6] | CLKOCKEN | ClocK Output Clock Enable Control |
0 = Clock Output Clock Disabled. | ||
1 = Clock Output Clock Enabled. | ||
[8] | I2C0CKEN | I2C0 Clock Enable Control |
0 = I2C0 Clock Disabled. | ||
1 = I2C0 Clock Enabled. | ||
[9] | I2C1CKEN | I2C1 Clock Enable Control |
0 = I2C1 Clock Disabled. | ||
1 = I2C1 Clock Enabled. | ||
[11] | ACMP0CKEN | ACMP0 Clock Enable Control |
0 = ACMP0 Clock Disabled. | ||
1 = ACMP0 Clock Enabled. | ||
[12] | SPI0CKEN | SPI0 Clock Enable Control |
0 = SPI0 Clock Disabled. | ||
1 = SPI0 Clock Enabled. | ||
[13] | SPI1CKEN | SPI1 Clock Enable Control |
0 = SPI1 Clock Disabled. | ||
1 = SPI1 Clock Enabled. | ||
[14] | SPI2CKEN | SPI2 Clock Enable Control |
0 = SPI2 Clock Disabled. | ||
1 = SPI2 Clock Enabled. | ||
[15] | SPI3CKEN | SPI3 Clock Enable Control |
0 = SPI3 Clock Disabled. | ||
1 = SPI3 Clock Enabled. | ||
[16] | UART0CKEN | UART0 Clock Enable Control |
0 = UART0 Clock Disabled. | ||
1 = UART0 Clock Enabled. | ||
[17] | UART1CKEN | UART1 Clock Enable Control |
0 = UART1 Clock Disabled. | ||
1 = UART1 Clock Enabled. | ||
[20] | PWM0CKEN | PWM0 Clock Enable Control |
0 = PWM0 Clock Disabled. | ||
1 = PWM0 Clock Enabled. | ||
[28] | ADCCKEN | Analog-digital-converter (ADC) Clock Enable Control |
0 = ADC Clock Disabled. | ||
1 = ADC Clock Enabled. | ||
[30] | SC0CKEN | SmartCard 0 Clock Enable Control |
0 = SmartCard 0 Clock Disabled. | ||
1 = SmartCard 0 Clock Enabled. | ||
[31] | SC1CKEN | SmartCard 1 Clock Enable Control |
0 = SmartCard 1 Clock Disabled. | ||
1 = SmartCard 1 Clock Enabled. |
CLK_T::APBDIV |
[0x0034] APB Clock Divider
Bits | Field | Descriptions |
---|---|---|
[2:0] | APB0DIV | APB0 Clock Divider |
APB0 PCLK0 can be divided from HCLK. | ||
000: PCLK0 = HCLK. | ||
001: PCLK0 = 1/2 HCLK. | ||
010: PCLK0 = 1/4 HCLK. | ||
011: PCLK0 = 1/8 HCLK. | ||
100: PCLK0 = 1/16 HCLK. | ||
Others: PCLK0 = HCLK. | ||
[6:4] | APB1DIV | APB1 Clock Divider |
APB1 PCLK1 can be divided from HCLK. | ||
000: PCLK1 = HCLK. | ||
001: PCLK1 = 1/2 HCLK. | ||
010: PCLK1 = 1/4 HCLK. | ||
011: PCLK1 = 1/8 HCLK. | ||
100: PCLK1 = 1/16 HCLK. | ||
Others: PCLK1 = HCLK. |
SYS_T::BATDIVCTL |
[0x0074] Battery Voltage Divider Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | BATDIV2EN | Battery voltage divide 2 Enable Bit |
This bit is used to enable/disable battery voltage divider function. | ||
0 = Battery voltage divide 2 function Disabled (default). | ||
1 = Battery voltage divide 2 function Enabled. |
UART_T::BAUD |
[0x0024] UART Baud Rate Divisor Register.
Bits | Field | Descriptions |
---|---|---|
[15:0] | BRD | Baud Rate Divider |
The field indicates the baud rate divider | ||
This filed is used in baud rate calculation | ||
The detail description is shown in UART Controller Baud Rate Generation. | ||
[31] | DIV16EN | Divider 16 Enable Control |
The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = UART_CLK/ [M * (BRD + 1)]; The default value of M is 16. | ||
0 = The equation of baud rate is UART_CLK / [ (BRD+1)]. | ||
1 = The equation of baud rate is UART_CLK / [16 * (BRD+1)]. | ||
Note: In IrDA mode, this bit must clear to 0. |
PWM_T::BNF |
[0x00c0] PWM0 Brake Noise Filter Register
Bits | Field | Descriptions |
---|---|---|
[0] | BRK0FEN | PWM0 Brake 0 Noise Filter Enable Bit |
0 = Noise filter of PWM0 Brake 0 Disabled. | ||
1 = Noise filter of PWM0 Brake 0 Enabled. | ||
[3:1] | BRK0FCS | Brake 0 Edge Detector Filter Clock Selection |
000 = Filter clock = HCLK. | ||
001 = Filter clock = HCLK/2. | ||
010 = Filter clock = HCLK/4. | ||
011 = Filter clock = HCLK/8. | ||
100 = Filter clock = HCLK/16. | ||
101 = Filter clock = HCLK/32. | ||
110 = Filter clock = HCLK/64. | ||
111 = Filter clock = HCLK/128. | ||
[6:4] | BRK0FCNT | Brake 0 Edge Detector Filter Count |
The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. | ||
[7] | BRK0PINV | Brake 0 Pin Inverse |
0 = The state of pin PWMx_BRAKE0 is passed to the negative edge Detector. | ||
1 = The inversed state of pin PWMx_BRAKE10 is passed to the negative edge Detector. | ||
[8] | BRK1FEN | PWM0 Brake 1 Noise Filter Enable Bit |
0 = Noise filter of PWM0 Brake 1 Disabled. | ||
1 = Noise filter of PWM0 Brake 1 Enabled. | ||
[11:9] | BRK1FCS | Brake 1 Edge Detector Filter Clock Selection |
000 = Filter clock = HCLK. | ||
001 = Filter clock = HCLK/2. | ||
010 = Filter clock = HCLK/4. | ||
011 = Filter clock = HCLK/8. | ||
100 = Filter clock = HCLK/16. | ||
101 = Filter clock = HCLK/32. | ||
110 = Filter clock = HCLK/64. | ||
111 = Filter clock = HCLK/128. | ||
[14:12] | BRK1FCNT | Brake 1 Edge Detector Filter Count |
The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. | ||
[15] | BRK1PINV | Brake 1 Pin Inverse |
0 = The state of pin PWMx_BRAKE1 is passed to the negative edge Detector. | ||
1 = The inversed state of pin PWMx_BRAKE1 is passed to the negative edge Detector. | ||
[16] | BK0SRC | Brake 0 Pin Source Select |
For PWM0 setting: | ||
0 = Brake 0 pin source come from PWM0_BRAKE0. | ||
1 = Brake 0 pin source come from PWM1_BRAKE0. | ||
For PWM1 setting: | ||
0 = Brake 0 pin source come from PWM1_BRAKE0. | ||
1 = Brake 0 pin source come from PWM0_BRAKE0. | ||
[24] | BK1SRC | Brake 1 Pin Source Select |
For PWM0 setting: | ||
0 = Brake 1 pin source come from PWM0_BRAKE1. | ||
1 = Brake 1 pin source come from PWM1_BRAKE1. | ||
For PWM1 setting: | ||
0 = Brake 1 pin source come from PWM1_BRAKE1. | ||
1 = Brake 1 pin source come from PWM0_BRAKE1. |
SYS_T::BODCTL |
[0x0064] Brown-out Detector Controller Register
Bits | Field | Descriptions |
---|---|---|
[0] | BODEN | Brown-out Detector Enable Bit (Write Protect) |
The default value is set by flash controller user configuration register CBODEN (CONFIG0 []) | ||
This Brown-out Detector only valid in Normal Mode. | ||
0 = Brown-out Detector function Disabled in Normal mode. | ||
1 = Brown-out Detector function Enabled in Normal mode. | ||
Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
Note2: LIRC must be enabled before enable BOD. | ||
[2] | BODIE | BOD Interrupt Enable Control (Write Protect) |
0 = Interrupt does not issue when BOD occurs in Normal Mode. | ||
1 = Interrupt issues when BOD occurs in Normal Mode. | ||
Note1: While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. | ||
Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[3] | BODREN | Brown-out Reset Enable Bit (Write Protect) |
The default value is set by flash controller user configuration register CBOV(CONFIG0[]) bit . | ||
0 = Brown-out RESET function Disabled in Normal Mode. | ||
1 = Brown-out RESET function Enabled in Normal Mode. | ||
Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). | ||
Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[4] | BODIF | Brown-out Detector Interrupt Flag |
0 = Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled. | ||
1 = When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. | ||
Note: Write 1 to clear this bit to 0. | ||
[6] | BODOUT | Brown-out Detector Output Status |
0 = Brown-out Detector output status is 0. | ||
It means the detected voltage is higher than BODVL setting or BODEN is 0. | ||
1 = Brown-out Detector output status is 1. | ||
It means the detected voltage is lower than BODVL setting | ||
If the BODEN is 0, BOD function disabled , this bit always responds 0. | ||
Note: This bit is ready-only. | ||
[7] | LVREN | Low Voltage Reset Enable Bit (Write Protect) |
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting | ||
LVR function is enabled by default. | ||
0 = Low Voltage Reset function Disabled. | ||
1 = Low Voltage Reset function Enabled. | ||
Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). | ||
Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
Note3: LIRC must be enabled before enable LVR. | ||
[8] | LPBODEN | Low Power Brown-out Detector Enable Bit (Write Protect) |
Low Power Brown-out Detector only valid in Power Down mode. | ||
0 = Low Power Brown-out Detector function Disabled in Power Down mode. | ||
1 = Low Power Brown-out Detector function Enabled in Power Down mode. | ||
Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
Note2: LIRC must be enabled before enable BOD. | ||
[9] | LPBODVL | Low Power Brown-out Detector Threshold Voltage Selection (Write Protect) |
Low Power Brown-out Detector only valid in Power Down mode. | ||
0 = Low Power Brown-Out Detector threshold voltage is 2.0V in Power Down mode. | ||
1 = Low Power Brown-Out Detector threshold voltage is 2.5V in Power Down mode. | ||
Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[10] | LPBODIE | Low Power BOD Interrupt Enable Control (Write Protect) |
Low Power Brown-out Detector only valid in Power Down mode. | ||
0 = Interrupt does not issue when LPBOD occurs in Power Down mode. | ||
1 = Interrupt issues when LPBOD occurs in Power Down mode | ||
Note1: While the LPBOD function is enabled (LPBODEN high) and LPBOD interrupt function is enabled (LPBODIE high), LPBOD will assert an interrupt if BODOUT is high | ||
Note2: This bit is write protected | ||
Refer to the SYS_REGLCTL register. | ||
[11] | LPBODREN | Low Power Brown-out Reset Enable Bit (Write Protect) |
Low Power Brown-out Detector only valid in Power Down mode. | ||
0 = Low power Brown-out Detector RESET function Disabled in Power Down mode. | ||
1 = Low Power Brown-out Detector RESET function Enabled in Power Down mode. | ||
Note1: While the Low power Brown-out Detector function is enabled (LPBODEN high) and LPBOD reset function is enabled (LPBODREN high), LPBOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). | ||
Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[15:12] | BODVL | Brown-out Detector Threshold Voltage Selection (Write Protect) |
The default value is set by flash controller user configuration register CBOV (CONFIG0[]). | ||
0000 = Brown-Out Detector threshold voltage is 1.7V. | ||
0001 = Brown-Out Detector threshold voltage is 1.8V. | ||
0010 = Brown-Out Detector threshold voltage is 1.9V. | ||
0011 = Brown-Out Detector threshold voltage is 2.0V. | ||
0100 = Brown-Out Detector threshold voltage is 2.1V. | ||
0101 = Brown-Out Detector threshold voltage is 2.2V. | ||
0110 = Brown-Out Detector threshold voltage is 2.3V. | ||
0111 = Brown-Out Detector threshold voltage is 2.4V. | ||
1000 = Brown-Out Detector threshold voltage is 2.5V. | ||
1001 = Brown-Out Detector threshold voltage is 2.6V. | ||
1010 = Brown-Out Detector threshold voltage is 2.7V. | ||
1011 = Brown-Out Detector threshold voltage is 2.8V. | ||
1100 = Brown-Out Detector threshold voltage is 2.9V. | ||
1101 = Brown-Out Detector threshold voltage is 3.0V. | ||
1110 = Brown-Out Detector threshold voltage is 3.1V. | ||
1111 = Reserved. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[19:16] | LPBOD20TRIM | Low power BOD 2.0 TRIM Value (Write Protect) |
This value is used to control BOD20 detect voltage level in power-down mode, nominal 2.0 V | ||
Higher trim value, higher detection voltage. | ||
Note: These bits are write protected. Refer to the SYS_REGLCTL register. | ||
[23:20] | LPBOD25TRIM | Low power BOD 2.5 TRIM Value (Write Protect) |
This value is used to control LPBOD25 detect voltage level in power-down mode, nominal 2.5 V | ||
Higher trim value, higher detection voltage. | ||
Note: These bits are write protected. Refer to the SYS_REGLCTL register. | ||
[26:24] | BODDGSEL | Brown-out Detector Output De-glitch Time Select (Write Protect) |
000 = BOD output is sampled by RC10K clock. | ||
001 = 4 system clock (HCLK). | ||
010 = 8 system clock (HCLK). | ||
011 = 16 system clock (HCLK). | ||
100 = 32 system clock (HCLK). | ||
101 = 64 system clock (HCLK). | ||
110 = 128 system clock (HCLK). | ||
111 = 256 system clock (HCLK). | ||
Note: These bits are write protected. Refer to the SYS_REGLCTL register. | ||
[30:28] | LVRDGSEL | LVR Output De-glitch Time Select (Write Protect) |
000 = Without de-glitch function. | ||
001 = 4 system clock (HCLK). | ||
010 = 8 system clock (HCLK). | ||
011 = 16 system clock (HCLK). | ||
100 = 32 system clock (HCLK). | ||
101 = 64 system clock (HCLK). | ||
110 = 128 system clock (HCLK). | ||
111 = 256 system clock (HCLK). | ||
Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
UART_T::BRCOMPAT |
[0x003c] UART Baud Rate Compensation Register.
Bits | Field | Descriptions |
---|---|---|
[8:0] | BRCOMPAT | Baud Rate Compensation Patten |
These 9 bits are used to define the relative bit is compensated or not | ||
BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit. | ||
[31] | BRCOMPDEC | Baud Rate Compensation Decrease |
0 = Positive (increase one module clock) compensation for each compensated bit. | ||
1 = Negative (decrease one module clock) compensation for each compensated bit. |
PWM_T::BRKCTL0_1 |
[0x00c8] PWM0 Brake Edge Detect Control Register 0_1
Bits | Field | Descriptions |
---|---|---|
[4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) |
0 = BKP0 pin as edge-detect brake source Disabled. | ||
1 = BKP0 pin as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) |
0 = BKP1 pin as edge-detect brake source Disabled. | ||
1 = BKP1 pin as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) |
0 = System Fail condition as edge-detect brake source Disabled. | ||
1 = System Fail condition as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) |
0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) |
0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) |
0 = System Fail condition as level-detect brake source Disabled. | ||
1 = System Fail condition as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) |
00 = PWM0 even channel brake function not affect channel output. | ||
01 = PWM0 even channel output tri-state when brake happened. | ||
10 = PWM0 even channel output low level when brake happened. | ||
11 = PWM0 even channel output high level when brake happened. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) |
00 = PWM0 odd channel brake function not affect channel output. | ||
01 = PWM0 odd channel output tri-state when brake happened. | ||
10 = PWM0 odd channel output low level when brake happened. | ||
11 = PWM0 odd channel output high level when brake happened. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. |
PWM_T::BRKCTL2_3 |
[0x00cc] PWM0 Brake Edge Detect Control Register 2_3
Bits | Field | Descriptions |
---|---|---|
[4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) |
0 = BKP0 pin as edge-detect brake source Disabled. | ||
1 = BKP0 pin as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) |
0 = BKP1 pin as edge-detect brake source Disabled. | ||
1 = BKP1 pin as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) |
0 = System Fail condition as edge-detect brake source Disabled. | ||
1 = System Fail condition as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) |
0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) |
0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) |
0 = System Fail condition as level-detect brake source Disabled. | ||
1 = System Fail condition as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) |
00 = PWM0 even channel brake function not affect channel output. | ||
01 = PWM0 even channel output tri-state when brake happened. | ||
10 = PWM0 even channel output low level when brake happened. | ||
11 = PWM0 even channel output high level when brake happened. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) |
00 = PWM0 odd channel brake function not affect channel output. | ||
01 = PWM0 odd channel output tri-state when brake happened. | ||
10 = PWM0 odd channel output low level when brake happened. | ||
11 = PWM0 odd channel output high level when brake happened. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. |
PWM_T::BRKCTL4_5 |
[0x00d0] PWM0 Brake Edge Detect Control Register 4_5
Bits | Field | Descriptions |
---|---|---|
[4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) |
0 = BKP0 pin as edge-detect brake source Disabled. | ||
1 = BKP0 pin as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) |
0 = BKP1 pin as edge-detect brake source Disabled. | ||
1 = BKP1 pin as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) |
0 = System Fail condition as edge-detect brake source Disabled. | ||
1 = System Fail condition as edge-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) |
0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) |
0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) |
0 = System Fail condition as level-detect brake source Disabled. | ||
1 = System Fail condition as level-detect brake source Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) |
00 = PWM0 even channel brake function not affect channel output. | ||
01 = PWM0 even channel output tri-state when brake happened. | ||
10 = PWM0 even channel output low level when brake happened. | ||
11 = PWM0 even channel output high level when brake happened. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) |
00 = PWM0 odd channel brake function not affect channel output. | ||
01 = PWM0 odd channel output tri-state when brake happened. | ||
10 = PWM0 odd channel output low level when brake happened. | ||
11 = PWM0 odd channel output high level when brake happened. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. |
RTC_T::CAL |
[0x0010] RTC Calendar Loading Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | DAY | 1-Day Calendar Digit (0~9) |
[5:4] | TENDAY | 10-Day Calendar Digit (0~3) |
[11:8] | MON | 1-Month Calendar Digit (0~9) |
[12] | TENMON | 10-Month Calendar Digit (0~1) |
[19:16] | YEAR | 1-Year Calendar Digit (0~9) |
[23:20] | TENYEAR | 10-Year Calendar Digit (0~9) |
ADC_T::CALCTL |
[0x0068] A/D Calibration Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | CALEN | Calibration Function Enable Bit |
Enable this bit to turn on the calibration function block. | ||
0 = Bypass calibration functional block. | ||
1 = Enabled calibration functional block. | ||
[1] | CALSTART | Calibration Functional Block Start |
0 = Stops calibration functional block. | ||
1 = Starts calibration functional block. | ||
Note: This bit is set by software and cleared by hardware; don't write 1 to this bit while CALEN (ADC_CALCTL[0]) = 0. | ||
[2] | CALDONE | Calibrate Functional Block Done |
0 = Not yet. | ||
1 = Selected calibration functional block complete. | ||
Note: This bit is set by hardware and auto cleared by hardware, This bit can also be cleared by software writing 1. | ||
[3] | CALSEL | Calibration Functional Block Selection |
0 = Load calibration functional block. | ||
1 = Calibration functional block. |
RTC_T::CALM |
[0x0020] RTC Calendar Alarm Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | DAY | 1-Day Calendar Digit of Alarm Setting (0~9) |
[5:4] | TENDAY | 10-Day Calendar Digit of Alarm Setting (0~3) |
[11:8] | MON | 1-Month Calendar Digit of Alarm Setting (0~9) |
[12] | TENMON | 10-Month Calendar Digit of Alarm Setting (0~1) |
[19:16] | YEAR | 1-Year Calendar Digit of Alarm Setting (0~9) |
[23:20] | TENYEAR | 10-Year Calendar Digit of Alarm Setting (0~9) |
ADC_T::CALWORD |
[0x006c] A/D Calibration Load word Register
Bits | Field | Descriptions |
---|---|---|
[6:0] | CALWORD | Calibration Word Bits |
Write to this register with the previous calibration word before load calibration action, read this register after calibration done. | ||
Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. |
RTC_T::CAMSK |
[0x0038] RTC Calendar Alarm Mask Register
Bits | Field | Descriptions |
---|---|---|
[0] | MDAY | Mask 1-Day Calendar Digit of Alarm Setting (0~9) |
[1] | MTENDAY | Mask 10-Day Calendar Digit of Alarm Setting (0~3) |
[2] | MMON | Mask 1-Month Calendar Digit of Alarm Setting (0~9) |
[3] | MTENMON | Mask 10-Month Calendar Digit of Alarm Setting (0~1) |
[4] | MYEAR | Mask 1-Year Calendar Digit of Alarm Setting (0~9) |
[5] | MTENYEAR | Mask 10-Year Calendar Digit of Alarm Setting (0~9) |
TIMER_T::CAP |
[0x0018] Timer Capture Data Register
Bits | Field | Descriptions |
---|---|---|
[23:0] | CAPDAT | Timer Capture Data Register |
When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 0, and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. | ||
When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 1, and the transition on Tx_EXT pin matched the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. | ||
Note: When edge transition defined by CAPEDGE (TIMERx_CTL[19:18]) is detected on Tx_EXT (x = 0 ~ 3) before CPU clears the CAPIF (TIMERxISR[1]) status, the timer keeps this value unchanged and CAPDATOF (TIMERx_INTSTS[5]) is set to 1. |
PWM_T::CAPCTL |
[0x0204] PWM0 Capture Control Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | CAPENn | Capture Function Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. | ||
1 = Capture function Enabled | ||
Capture latched the PWM0 counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). | ||
[13:8] | CAPINVn | Capture Inverter Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Capture source inverter Disabled. | ||
1 = Capture source inverter Enabled. Reverse the input signal from GPIO. | ||
[21:16] | RCRLDENn | Rising Capture Reload Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Rising capture reload counter Disabled. | ||
1 = Rising capture reload counter Enabled. | ||
[29:24] | FCRLDENn | Falling Capture Reload Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Falling capture reload counter Disabled. | ||
1 = Falling capture reload counter Enabled. |
PWM_T::CAPIEN |
[0x0250] PWM0 Capture Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | CAPRIENn | PWM0 Capture Rising Latch Interrupt Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Capture rising edge latch interrupt Disabled. | ||
1 = Capture rising edge latch interrupt Enabled. | ||
[13:8] | CAPFIENn | PWM0 Capture Falling Latch Interrupt Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Capture falling edge latch interrupt Disabled. | ||
1 = Capture falling edge latch interrupt Enabled. |
PWM_T::CAPIF |
[0x0254] PWM0 Capture Interrupt Flag Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | CAPRIFn | PWM0 Capture Rising Latch Interrupt Flag |
This bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. | ||
0 = No capture rising latch condition happened. | ||
1 = Capture rising latch condition happened, this flag will be set to high. | ||
[13:8] | CAPFIFn | PWM0 Capture Falling Latch Interrupt Flag |
This bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. | ||
0 = No capture falling latch condition happened. | ||
1 = Capture falling latch condition happened, this flag will be set to high. |
PWM_T::CAPINEN |
[0x0200] PWM0 Capture Input Enable Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | CAPINENn | Capture Input Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = PWM0 Channel capture input path Disabled | ||
The input of PWM0 channel capture function is always regarded as 0. | ||
1 = PWM0 Channel capture input path Enabled | ||
The input of PWM0 channel capture function comes from correlative multifunction pin. |
PWM_T::CAPSTS |
[0x0208] PWM0 Capture Status Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | CRIFOVn | Capture Rising Interrupt Flag Overrun Status (Read Only) |
This flag indicates if rising latch happened when the corresponding CAPRIF is 1 | ||
Each bit n controls the corresponding PWM0 channel n. | ||
Note: This bit will be cleared automatically when user clear corresponding CAPRIF. | ||
[13:8] | CFIFOVn | Capture Falling Interrupt Flag Overrun Status (Read Only) |
This flag indicates if falling latch happened when the corresponding CAPFIF is 1 | ||
Each bit n controls the corresponding PWM0 channel n. | ||
Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
PDMA_CH_T::CCNTn |
[0x001c] PDMA channel n Current Transfer Count Register
Bits | Field | Descriptions |
---|---|---|
[15:0] | CCNT | PDMA Current Count Bits (Read Only) |
This field indicates the current remained transfer count of PDMA. | ||
Note: This field value will be cleared to 0 when user sets SWRST (PDMA_CTLn[1],n=1~4) to 1. |
PDMA_CH_T::CDAn |
CLK_T::CDLOWB |
[0x0048] Clock Frequency Detector Lower Boundary Register
Bits | Field | Descriptions |
---|---|---|
[10:0] | LOWERBD | HXT Clock Frequency Detector Lower Boundary |
The bits define the low value of frequency monitor window. | ||
When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. |
CLK_T::CDUPB |
[0x0044] Clock Frequency Detector Upper Boundary Register
Bits | Field | Descriptions |
---|---|---|
[10:0] | UPERBD | HXT Clock Frequency Detector Upper Boundary |
The bits define the high value of frequency monitor window. | ||
When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. |
DMA_CRC_T::CHECKSUM |
ADC_T::CHEN |
[0x004c] A/D Channel Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | CHEN0 | Analog Input Channel 0 Enable Bit (Convert Input Voltage From PA.0 ) |
0 = Channel 0 Disabled. | ||
1 = Channel 0 Enabled. | ||
Note: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored. | ||
[1] | CHEN1 | Analog Input Channel 1 Enable Bit (Convert Input Voltage From PA.1 ) |
0 = Channel 1 Disabled. | ||
1 = Channel 1 Enabled. | ||
[2] | CHEN2 | Analog Input Channel 2 Enable Bit (Convert Input Voltage From PA.2 ) |
0 = Channel 2 Disabled. | ||
1 = Channel 2 Enabled. | ||
[3] | CHEN3 | Analog Input Channel 3 Enable Bit (Convert Input Voltage From PA.3 ) |
0 = Channel 3 Disabled. | ||
1 = Channel 3 Enabled. | ||
[4] | CHEN4 | Analog Input Channel 4 Enable Bit (Convert Input Voltage From PA.4 ) |
0 = Channel 4 Disabled. | ||
1 = Channel 4 Enabled. | ||
[5] | CHEN5 | Analog Input Channel 5 Enable Bit (Convert Input Voltage From PA.5 ) |
0 = Channel 5 Disabled. | ||
1 = Channel 5 Enabled. | ||
[6] | CHEN6 | Analog Input Channel 6 Enable Bit (Convert Input Voltage From PA.6 ) |
0 = Channel 6 Disabled. | ||
1 = Channel 6 Enabled. | ||
[7] | CHEN7 | Analog Input Channel 7 Enable Bit (Convert Input Voltage From PA.7 ) |
0 = Channel 7 Disabled. | ||
1 = Channel 7 Enabled. | ||
[12] | CHEN12 | Analog Input Channel 12 Enable Bit (Convert VBG) |
0 = Channel 12 Disabled. | ||
1 = Channel 12 Enabled. | ||
[13] | CHEN13 | Analog Input Channel 13 Enable Bit (Convert VBAT) |
0 = Channel 13 Disabled. | ||
1 = Channel 13 Enabled. | ||
[14] | CHEN14 | Analog Input Channel 14 Enable Bit (Convert VTEMP) |
0 = Channel 14 Disabled. | ||
1 = Channel 14 Enabled. | ||
[15] | CHEN15 | Analog Input Channel 15 Enable Bit (Convert Int_VREF) |
0 = Channel 15 Disabled. | ||
1 = Channel 15 Enabled. | ||
[16] | CHEN16 | Analog Input Channel 16 Enable Bit (Convert AVDD) |
0 = Channel 16 Disabled. | ||
1 = Channel 16 Enabled. | ||
[17] | CHEN17 | Analog Input Channel 17 Enable Bit (Convert AVSS) |
0 = Channel 17 Disabled. | ||
1 = Channel 17 Enabled. |
CLK_T::CLKDCTL |
[0x0038] Clock Fail Detector Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | HXTFDEN | HXT Clock Fail Detector Enable Bit |
0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail Detector Disabled. | ||
1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail Detector Enabled. | ||
[1] | LXTFDEN | LXT Clock Fail Detector Enable Bit |
0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail Detector Disabled. | ||
1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail Detector Enabled. | ||
[2] | HXTFQDEN | HXT Clock Frequency Monitor Enable Bit |
0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. | ||
1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. |
CLK_T::CLKDIE |
[0x003c] Clock Fail Detector Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | HXTFIEN | HXT Clock Fail Interrupt Enable Bit |
0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. | ||
1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. | ||
[1] | LXTFIEN | LXT Clock Fail Interrupt Enable Bit |
0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. | ||
1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. | ||
[2] | HXTFQIEN | HXT Clock Frequency Monitor Interrupt Enable Bit |
0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. | ||
1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. |
I2C_T::CLKDIV |
SPI_T::CLKDIV |
[0x0008] SPI Clock Divider Register
Bits | Field | Descriptions |
---|---|---|
[7:0] | DIVIDER | Clock Divider |
The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_CLK | ||
The desired frequency is obtained according to the following equation: | ||
Where | ||
is the SPI peripheral clock source | ||
It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18). |
CLK_T::CLKDIV0 |
[0x001c] Clock Divider Number Register 0
Bits | Field | Descriptions |
---|---|---|
[3:0] | HCLKDIV | HCLK Clock Divide Number From HCLK Clock Source |
HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). | ||
[11:8] | UART0DIV | UART0 Clock Divide Number From UART Clock Source |
The UART0 clock frequency = (UART0 Clock Source frequency) / (UART0DIV + 1). | ||
[15:12] | UART1DIV | UART1 Clock Divide Number From UART Clock Source |
The UART1 clock frequency = (UART1 Clock Source frequency) / (UART1DIV + 1). | ||
[23:16] | ADCDIV | ADC Clock Divide Number From ADC Clock Source |
ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1). | ||
[31:28] | SC0DIV | SC0 Clock Divide Number From SC0 Clock Source |
SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). |
CLK_T::CLKDIV1 |
[0x0020] Clock Divider Number Register 1
Bits | Field | Descriptions |
---|---|---|
[3:0] | SC1DIV | SC 1 Clock Divide Number From SC 1 Clock Source |
The SC 1 clock frequency = (SC 1 Clock Source frequency) / (SC1DIV + 1). | ||
[11:8] | TMR0DIV | Timer0 Clock Divide Number From Timer0 Clock Source |
The Timer0 clock frequency = (Timer0 Clock Source frequency) / (TMR0DIV + 1). | ||
[15:12] | TMR1DIV | Timer1 Clock Divide Number From Timer1 Clock Source |
The Timer1 clock frequency = (Timer1 Clock Source frequency) / (TMR1DIV + 1). | ||
[19:16] | TMR2DIV | Timer2 Clock Divide Number From Timer2 Clock Source |
The Timer2 clock frequency = (Timer2 Clock Source frequency) / (TMR2DIV + 1). | ||
[23:20] | TMR3DIV | Timer3 Clock Divide Number From Timer3 Clock Source |
The Timer3 clock frequency = (Timer3 Clock Source frequency) / (TMR3DIV + 1). |
CLK_T::CLKDSTS |
[0x0040] Clock Fail Detector Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | HXTFIF | HXT Clock Fail Interrupt Flag |
0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. | ||
1 = 4~32 MHz external high speed crystal oscillator (HXT) clock stops. | ||
Note: Write 1 to clear the bit to 0. | ||
[1] | LXTFIF | LXT Clock Fail Interrupt Flag |
0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. | ||
1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. | ||
Note: Write 1 to clear the bit to 0. | ||
[2] | HXTFQIF | HXT Clock Frequency Monitor Interrupt Flag |
0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. | ||
1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. | ||
Note: Write 1 to clear the bit to 0. |
RTC_T::CLKFMT |
[0x0014] RTC Time Scale Selection Register
Bits | Field | Descriptions |
---|---|---|
[0] | 24HEN | 24-hour / 12-hour Time Scale Selection |
Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale | ||
0 = 12-hour time scale with AM and PM indication selected. | ||
1 = 24-hour time scale selected. |
CLK_T::CLKOCTL |
[0x0028] Clock Output Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | FREQSEL | Clock Output Frequency Selection |
The formula of output frequency is | ||
Fout = Fin/2(N+1). | ||
Fin is the input clock frequency. | ||
Fout is the frequency of divider output clock. | ||
N is the 4-bit value of FREQSEL[3:0]. | ||
[4] | CLKOEN | Clock Output Enable Bit |
0 = Clock Output function Disabled. | ||
1 = Clock Output function Enabled. | ||
[5] | DIV1EN | Clock Output Divide One Enable Bit |
0 = Clock Output will output clock with source frequency divided by FREQSEL. | ||
1 = Clock Output will output clock with source frequency. |
PWM_T::CLKPSC0_1 |
[0x0014] PWM0 Clock Pre-Scale Register 0_1
Bits | Field | Descriptions |
---|---|---|
[11:0] | CLKPSC | PWM0 Counter Clock Pre-scale |
The clock of PWM0 counter is decided by clock prescaler | ||
Each PWM0 pair share one PWM0 counter clock prescaler | ||
The clock of PWM0 counter is divided by (CLKPSC+ 1) |
PWM_T::CLKPSC2_3 |
[0x0018] PWM0 Clock Pre-Scale Register 2_3
Bits | Field | Descriptions |
---|---|---|
[11:0] | CLKPSC | PWM0 Counter Clock Pre-scale |
The clock of PWM0 counter is decided by clock prescaler | ||
Each PWM0 pair share one PWM0 counter clock prescaler | ||
The clock of PWM0 counter is divided by (CLKPSC+ 1) |
PWM_T::CLKPSC4_5 |
[0x001c] PWM0 Clock Pre-Scale Register 4_5
Bits | Field | Descriptions |
---|---|---|
[11:0] | CLKPSC | PWM0 Counter Clock Pre-scale |
The clock of PWM0 counter is decided by clock prescaler | ||
Each PWM0 pair share one PWM0 counter clock prescaler | ||
The clock of PWM0 counter is divided by (CLKPSC+ 1) |
CLK_T::CLKSEL0 |
[0x0010] Clock Source Select Control Register 0
Bits | Field | Descriptions |
---|---|---|
[2:0] | HCLKSEL | HCLK Clock Source Selection (Write Protect) |
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. | ||
000 = Clock source from HXT. | ||
001 = Clock source from LXT. | ||
010 = Clock source from PLL. | ||
011 = Clock source from LIRC. | ||
100= Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
Others = Clock source from MIRC. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[3] | HIRCSEL | HIRC Source Selection |
0 = Clock source from HIRC0 (12~16MHz). | ||
1 = Clock source from HIRC1 (36MHz). | ||
[4] | ISPSEL | ISP Clock Source Selection |
0 = Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
1 = Clock source from MIRC. |
CLK_T::CLKSEL1 |
[0x0014] Clock Source Select Control Register 1
Bits | Field | Descriptions |
---|---|---|
[2:0] | UART0SEL | UART0 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from PLL. | ||
011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
[4] | PWM0SEL | PWM0 Clock Source Selection |
0 = Clock source from PLL. | ||
1 = Clock source from PCLK0. | ||
[10:8] | TMR0SEL | Timer0 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
011 = Clock source from external clock pin. | ||
100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
Others = Clock source from HCLK. | ||
[14:12] | TMR1SEL | Timer1 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
011 = Clock source from external clock pin. | ||
100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
Others = Clock source from HCLK. | ||
[21:19] | ADCSEL | ADC Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from PLL. | ||
011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
Others = Clock source from HCLK. | ||
[25:24] | SPI0SEL | SPI0 Clock Source Selection |
00 = Clock source from PLL. | ||
01 = Clock source from HCLK. | ||
10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
[27:26] | SPI2SEL | SPI2 Clock Source Selection |
00 = Clock source from PLL. | ||
01 = Clock source from HCLK. | ||
10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
[29:28] | WDTSEL | WDT Clock Source Selection |
00 = reserved. | ||
01 = Clock source from LXT. | ||
10 = Clock source from HCLK/2048. | ||
11 = Clock source from LIRC | ||
[31:30] | WWDTSEL | WDT Clock Source Selection |
00 = reserved. | ||
01 = reserved. | ||
10 = Clock source from HCLK/2048. | ||
11 = Clock source from LIRC |
CLK_T::CLKSEL2 |
[0x0018] Clock Source Select Control Register 2
Bits | Field | Descriptions |
---|---|---|
[2:0] | UART1SEL | UART1 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from PLL. | ||
011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
[6:4] | CLKOSEL | Clock Divider Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from HCLK. | ||
011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
[10:8] | TMR2SEL | Timer2 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
011 = Clock source from external clock pin. | ||
100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC) | ||
Others = Clock source from HCLK. | ||
[14:12] | TMR3SEL | Timer3 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
011 = Clock source from external clock pin. | ||
100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
Others = Clock source from HCLK. | ||
[18:16] | SC0SEL | SC0 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from PLL. | ||
010 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
011 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
Others = Clock source from HCLK. | ||
[22:20] | SC1SEL | SC1 Clock Source Selection |
000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
001 = Clock source from PLL. | ||
010 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
011 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
Others = Clock source from HCLK. | ||
[25:24] | SPI1SEL | SPI1 Clock Source Selection |
00 = Clock source from PLL. | ||
01 = Clock source from HCLK. | ||
10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
[27:26] | SPI3SEL | SPI3 Clock Source Selection |
00 = Clock source from PLL. | ||
01 = Clock source from HCLK. | ||
10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. |
PWM_T::CLKSRC |
[0x0010] PWM0 Clock Source Register
Bits | Field | Descriptions |
---|---|---|
[2:0] | ECLKSRC0 | PWM0_CH01 External Clock Source Select |
000 = PWMx_CLK, x denotes 0 or 1. | ||
001 = TIMER0 overflow. | ||
010 = TIMER1 overflow. | ||
011 = TIMER2 overflow. | ||
100 = TIMER3 overflow. | ||
Others = Reserved. | ||
[10:8] | ECLKSRC2 | PWM0_CH23 External Clock Source Select |
000 = PWMx_CLK, x denotes 0 or 1. | ||
001 = TIMER0 overflow. | ||
010 = TIMER1 overflow. | ||
011 = TIMER2 overflow. | ||
100 = TIMER3 overflow. | ||
Others = Reserved. | ||
[18:16] | ECLKSRC4 | PWM0_CH45 External Clock Source Select |
000 = PWMx_CLK, x denotes 0 or 1. | ||
001 = TIMER0 overflow. | ||
010 = TIMER1 overflow. | ||
011 = TIMER2 overflow. | ||
100 = TIMER3 overflow. | ||
Others = Reserved. |
TIMER_T::CMP |
[0x0008] Timer Compare Register
Bits | Field | Descriptions |
---|---|---|
[23:0] | CMPDAT | Timer Compared Value |
CMPDAT is a 24-bit compared value register | ||
When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1. | ||
Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). | ||
Note1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state. | ||
Note2: When the timer is operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is 11), the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. | ||
Note3: When the timer is not operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is not 11), the 24-bit up counter will restart counting from 0 and use the newest CMPDAT value as the timer compared value when user writes a new value into the CMPDAT field | ||
In addition, the prescale counter will be reloaded. |
ADC_T::CMP0 |
[0x0050] A/D Compare Register 0
Bits | Field | Descriptions |
---|---|---|
[0] | ADCMPEN | A/D Compare Enable Bit |
Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register. | ||
0 = Compare function Disabled. | ||
1 = Compare function Enabled. | ||
Note: When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit. | ||
[1] | ADCMPIE | A/D Compare Interrupt Enable Bit |
If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate. | ||
0 = Compare function interrupt Disabled. | ||
1 = Compare function interrupt Enabled. | ||
[2] | CMPCOND | Compare Condition |
0 = Set the compare condition as that when a A/D conversion result is less than the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
1 = Set the compare condition as that when a A/D conversion result is more than or equal to the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
Note: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
[7:3] | CMPCH | Compare Channel Selection |
Set this field to select which channel's result to be compared. | ||
Note: Valid setting of this field is channel 0~17, but channel 8~12 are reserved. | ||
[11:8] | CMPMCNT | Compare Match Count |
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. | ||
Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
[27:16] | CMPDAT | Comparison Data |
The 12 bits data is used to compare with conversion result of specified channel | ||
Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. |
ADC_T::CMP1 |
[0x0054] A/D Compare Register 1
Bits | Field | Descriptions |
---|---|---|
[0] | ADCMPEN | A/D Compare Enable Bit |
Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register. | ||
0 = Compare function Disabled. | ||
1 = Compare function Enabled. | ||
Note: When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit. | ||
[1] | ADCMPIE | A/D Compare Interrupt Enable Bit |
If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate. | ||
0 = Compare function interrupt Disabled. | ||
1 = Compare function interrupt Enabled. | ||
[2] | CMPCOND | Compare Condition |
0 = Set the compare condition as that when a A/D conversion result is less than the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
1 = Set the compare condition as that when a A/D conversion result is more than or equal to the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
Note: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
[7:3] | CMPCH | Compare Channel Selection |
Set this field to select which channel's result to be compared. | ||
Note: Valid setting of this field is channel 0~17, but channel 8~12 are reserved. | ||
[11:8] | CMPMCNT | Compare Match Count |
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. | ||
Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
[27:16] | CMPDAT | Comparison Data |
The 12 bits data is used to compare with conversion result of specified channel | ||
Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. |
PWM_T::CMPBUF0 |
PWM_T::CMPBUF1 |
PWM_T::CMPBUF2 |
PWM_T::CMPBUF3 |
PWM_T::CMPBUF4 |
PWM_T::CMPBUF5 |
PWM_T::CMPDAT |
[0x0050] PWM0 Comparator Register 0,1,2,3,4,5
Bits | Field | Descriptions |
---|---|---|
[15:0] | CMPDAT | PWM0 Comparator Register |
CMPDAT use to compare with CNTR to generate PWM0 waveform, interrupt and trigger ADC. | ||
In independent mode, CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point. | ||
In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM0_CH0 and PWM0_CH1, PWM0_CH2 and PWM0_CH3, PWM0_CH4 and PWM0_CH5. |
TIMER_T::CNT |
[0x0014] Timer Counter Data Register
Bits | Field | Descriptions |
---|---|---|
[23:0] | CNT | Timer Counter Data (Read) |
This field can reflect the internal 24-bit timer counter value or external event input counter value from Tx (x=0~3) pin. | ||
Counter Reset (Write) | ||
User can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter | ||
This reset operation wouldn't affect any other timer control registers and circuit | ||
After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TIMERx_CTL register setting. | ||
[31] | RSTACT | Reset Active |
This bit indicates if the counter reset operation active. | ||
When user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0 | ||
At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress | ||
Once the counter reset operation done, timer clear this bit to 0 automatically. | ||
0 = Reset operation is done. | ||
1 = Reset operation triggered by writing TIMERx_CNT is in progress. | ||
Note: This bit is read only. Write operation wouldn't take any effect. |
PWM_T::CNT |
[0x0090] PWM0 Counter Register 0,2,4
Bits | Field | Descriptions |
---|---|---|
[15:0] | CNT | PWM0 Data Register (Read Only) |
User can monitor CNTR to know the current value in 16-bit period counter. | ||
[16] | DIRF | PWM0 Direction Indicator Flag (Read Only) |
0 = Counter is Down count. | ||
1 = Counter is UP count. |
WWDT_T::CNT |
PWM_T::CNTCLR |
[0x0024] PWM0 Clear Counter Register
Bits | Field | Descriptions |
---|---|---|
[0] | CNTCLR0 | Clear PWM0 Counter Control Bit 0 |
It is automatically cleared by hardware. | ||
0 = No effect. | ||
1 = Clear 16-bit PWM0 counter to 0000H. | ||
[2] | CNTCLR2 | Clear PWM0 Counter Control Bit 2 |
It is automatically cleared by hardware. | ||
0 = No effect. | ||
1 = Clear 16-bit PWM0 counter to 0000H. | ||
[4] | CNTCLR4 | Clear PWM0 Counter Control Bit 4 |
It is automatically cleared by hardware. | ||
0 = No effect. | ||
1 = Clear 16-bit PWM0 counter to 0000H. |
PWM_T::CNTEN |
[0x0020] PWM0 Counter Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | CNTEN0 | PWM0 Counter Enable Bit 0 |
0 = PWM0 Counter0_1 and clock prescaler0 Stop Running. | ||
1 = PWM0 Counter0_1 and clock prescaler0 Start Running. | ||
[2] | CNTEN2 | PWM0 Counter Enable Bit 2 |
0 = PWM0 Counter2_3 and clock prescaler2 Stop Running. | ||
1 = PWM0 Counter2_3 and clock prescaler2 Start Running. | ||
[4] | CNTEN4 | PWM0 Counter Enable Bit 4 |
0 = PWM0 Counter4_5 and clock prescaler4 Stop Running. | ||
1 = PWM0 Counter4_5 and clock prescaler4 Start Running. |
PDMA_CH_T::CNTn |
[0x000c] PDMA channel n Transfer Count Register
Bits | Field | Descriptions |
---|---|---|
[15:0] | TCNT | PDMA Transfer Count Bits |
This field indicates a 16-bit transfer count number of PDMA. | ||
[31:16] | PCNTITH | PDMA Periodic Count Interrupt Threshold |
This field indicates how many data transferred to generate periodic interrupt | ||
Note: write 0 to this field to disable this function. |
PDMA_CH_T::CSAn |
DMA_CRC_T::CTL |
[0x0000] CRC Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | CRCEN | CRC Channel Enable Bit |
0 = No effect. | ||
1 = CRC operation Enabled. | ||
When operating in CRC DMA mode (TRIGEN (CRC_CTL[23]) = 1), if user clears this bit, the PDMA operation will be continuous until all CRC DMA operation is done, and the TRIGEN bit will keep 1 until all CRC DMA operation done | ||
But in this case, the CRCTDIF (CRC_DMAINTSTS[1]) flag will be inactive, user can read CRC checksum result only if TRIGEN clears to 0 | ||
When operating in CRC DMA mode (TRIGEN (CRC_CTL[23]) = 1), if user wants to stop the transfer immediately, user can write 1 to CRCRST (CRC_CTL[1]) bit to stop the transmission. | ||
[1] | CRCRST | CRC Engine Reset Bit |
0 = No effect. | ||
1 = Reset the internal CRC state machine and internal buffer | ||
The others contents of CRC_CTL register will not be cleared. | ||
Note1: This bit will be cleared automatically. | ||
Note2: When operating in CPU mode, setting this bit will reload the seed value from CRC_SEED register as checksum initial value. | ||
[23] | TRIGEN | Trigger Enable Bit |
This bit is used to trigger the CRC DMA transfer. | ||
0 = No effect. | ||
1 = CRC DMA data read or write transfer Enabled. | ||
Note1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_DAT register. | ||
Note2: When CRC DMA transfer completed, this bit will be cleared automatically. | ||
Note3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped | ||
User must reset all DMA channel before trigger DMA again. | ||
[24] | DATREV | Write Data Bit Order Reverse |
This bit is used to enable the bit order reverse function for writing data value in CRC_DTA register. | ||
0 = Bit order reverse for CRC data write in Disabled. | ||
1 = Bit order reverse for CRC data write in Enabled (per byte). | ||
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC data write in is 0x55DD33BB. | ||
[25] | CHKSREV | Checksum Bit Order Reverse |
This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. | ||
0 = Bit order reverse for CRC checksum Disabled. | ||
1 = Bit order reverse for CRC checksum Enabled. | ||
Note: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB | ||
[26] | DATFMT | Write Data 1's Complement |
This bit is used to enable the 1's complement function for write data value in CRC_DTA register. | ||
0 = 1's complement for CRC writes data in Disabled. | ||
1 = 1's complement for CRC writes data in Enabled. | ||
[27] | CHKSFMT | Checksum 1's Complement |
This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. | ||
0 = 1's complement for CRC checksum Disabled. | ||
1 = 1's complement for CRC checksum Enabled. | ||
[29:28] | DATLEN | CPU Write Data Length |
This field indicates the CPU write data length only when operating in CPU mode. | ||
00 = The write data length is 8-bit mode. | ||
01 = The write data length is 16-bit mode. | ||
10 = The write data length is 32-bit mode. | ||
11 = Reserved. | ||
Note1: This field is only valid when operating in CPU mode. | ||
Note2: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA [15:0]. | ||
[31:30] | CRCMODE | CRC Polynomial Mode |
This field indicates the CRC operation polynomial mode. | ||
00 = CRC-CCITT Polynomial Mode. | ||
01 = CRC-8 Polynomial Mode. | ||
10 = CRC-16 Polynomial Mode. | ||
11 = CRC-32 Polynomial Mode. |
TIMER_T::CTL |
[0x0000] Timer Control and Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | CNTEN | Timer Counting Enable Bit |
0 = Stops/Suspends counting. | ||
1 = Starts counting. | ||
Note1: In stop status, set CNTEN to 1 enables 24-bit counter keeps up counting from the last stop counting value. | ||
Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE (TIMERx_CTL[5:4]) = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated. | ||
Note3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time. | ||
[1] | RSTCNT | Timer Counter Reset Bit |
Setting this bit will reset the internal 8-bit prescale counter, 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0. | ||
0 = No effect. | ||
1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit. | ||
Note: This bit will be auto cleared and takes at least 3 TIMERx_CLK clock cycles. | ||
[2] | WKEN | Wake-up Function Enable Bit |
If this bit is set to 1, while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1, the timer interrupt signal will generate a wake-up trigger event to CPU. | ||
0 = Wake-up function Disabled if timer interrupt signal generated. | ||
1 = Wake-up function Enabled if timer interrupt signal generated. | ||
[3] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Bit |
0 = ICE debug mode acknowledgement affects TIMER counting. | ||
Timer counter will be held while CPU is held by ICE. | ||
1 = ICE debug mode acknowledgement Disabled. | ||
Timer counter will keep going no matter CPU is held by ICE or not. | ||
[5:4] | OPMODE | Timer Counting Mode Selection |
00 = The Timer controller is operated in One-shot mode. | ||
01 = The Timer controller is operated in Periodic mode. | ||
10 = The Timer controller is operated in Toggle-output mode. | ||
11 = The Timer controller is operated in Continuous Counting mode. | ||
[7] | ACTSTS | Timer Active Status Bit (Read Only) |
This bit indicates the 24-bit up counter status. | ||
0 = 24-bit up counter is not active. | ||
1 = 24-bit up counter is active. | ||
[8] | TRGADC | Trigger ADC Enable Bit |
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC. | ||
0 = Timer interrupt trigger ADC Disabled. | ||
1 = Timer interrupt trigger ADC Enabled. | ||
Note: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger ADC. | ||
If TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger ADC. | ||
[10] | TRGPDMA | Timer Trigger PDMA Enable Bit |
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA. | ||
0 = Timer interrupt trigger PWM Disabled. | ||
1 = Timer interrupt trigger PWM Enabled. | ||
Note: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger PWM. | ||
If TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger PWM. | ||
[11] | TRGSSEL | Trigger Source Selection |
If this bit is set to 1, capture interrupt can trigger ADC, PDMA and PWM | ||
Otherwise, time-out interrupt can trigger ADC, PDMA and PWM. | ||
0 = Time-out interrupt is used to trigger ADC, PDMA and PWM. | ||
1 = Capture interrupt is used to trigger ADC, PDMA and PWM. | ||
[12] | EXTCNTEN | Event Counter Mode Enable Bit |
This bit is for external counting pin function enabled. | ||
0 = Event counter mode Disabled. | ||
1 = Event counter mode Enabled. | ||
Note: When timer is used as an event counter, this bit should be set to 1 and HCLK as timer clock source. | ||
[13] | CNTPHASE | Timer External Count Phase |
This bit indicates the detection phase of external counting pin Tx (x= 0~3). | ||
0 = A Falling edge of external counting pin will be counted. | ||
1 = A Rising edge of external counting pin will be counted. | ||
[14] | CNTDBEN | Timer Counter Pin De-bounce Enable Bit |
0 = Tx (x= 0~3) pin de-bounce Disabled. | ||
1 = Tx (x= 0~3) pin de-bounce Enabled. | ||
Note: If this bit is set to 1, the edge detection of Tx pin is detected with de-bounce circuit. | ||
[16] | CAPEN | Timer External Capture Pin Enable Bit |
This bit enables the Tx_EXT pin. | ||
0 = Tx_EXT (x= 0~3) pin Disabled. | ||
1 = Tx_EXT (x= 0~3) pin Enabled. | ||
Note1: For TIMERx_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEN will be forced to low and the TC pin transition is ignored (where x = 0 or 2). | ||
Note2: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEN will be forced to high (where x = 0 or 2). | ||
[17] | CAPFUNCS | Capture Function Selection |
0 = External Capture Mode Enabled. | ||
1 = External Reset Mode Enabled. | ||
Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value. | ||
Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value. | ||
Note3: For TIMERx+1_CTL (x = 0 or 2), if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPFUNCS will be forced to low. | ||
[19:18] | CAPEDGE | Timer External Capture Pin Edge Detection |
For timer counter reset function and free-counting mode of timer capture function, the configurations are: | ||
00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected. | ||
10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
11 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
For trigger-counting mode of timer capture function, the configurations are: | ||
00 = 1st falling edge on TC pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting. | ||
01 = 1st rising edge on TC pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting. | ||
10 = Falling edge on TC pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting. | ||
11 = Rising edge on TC pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting. | ||
Note: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEDGE will be forced to 11 (where x = 0 or 2). | ||
[20] | CAPCNTMD | Timer Capture Counting Mode Selection |
This bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high. | ||
If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by OPMODE (TIMERx_CTL[5:4]) field | ||
When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and the transition of TC pin matches the CAPEDGE (TIMERx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TIMERx_CAP. | ||
If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0 | ||
When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting | ||
And then if the transition of external pin matches the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting | ||
And its value will be saved into register TIMERx_CAP. | ||
0 = Capture with free-counting timer mode. | ||
1 = Capture with trigger-counting timer mode. | ||
Note: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set, the CAPCNTMD will be forced to high, the capture with Trigger-counting Timer mode (where x = 0 or 2). | ||
[22] | CAPDBEN | Timer External Capture Pin De-bounce Enable Bit |
0 = Tx_EXT (x= 0~3) pin de-bounce Disabled. | ||
1 = Tx_EXT (x= 0~3) pin de-bounce Enabled. | ||
Note1: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. | ||
Note2: For Timer 1 and 3, when INTRTGEN (TIMERx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low. | ||
[23] | CMPCTL | Timer Compared Mode Selection |
0 = The behavior selection in one-shot, periodic or Toggle-output mode Disabled. | ||
When user updates CMPDAT (TIMERx_CMP) while timer is running in One-shot, Periodic or Toggle-output mode, CNT (TIMERx_CNT) will be reset to default value. | ||
1 = The behavior selection in one-shot, periodic or Toggle-output mode Enabled. | ||
When user updates CMPDAT (TIMERx_CMP) while timer is running in One-shot, Periodic or Toggle-output mode, the limitations as bellows list, | ||
If updated CMPDAT (TIMERx_CMP) value > CNT (TIMERx_CNT), CMPDAT (TIMERx_CMP) will be updated and CNT (TIMERx_CNT) keep running continually. | ||
If updated CMPDAT (TIMERx_CMP) value = CNT (TIMERx_CNT), timer time-out interrupt will be asserted immediately. | ||
If updated CMPDAT (TIMERx_CMP) value < CNT (TIMERx_CNT), CNT (TIMERx_CNT) will be reset to default value | ||
At the same time, prescale counter reloaded. | ||
[24] | INTRTGEN | Inter-timer Trigger Function Enable Bit |
If INTRTGEN is set to 1 TIMERx (x = 0 or 2), TIMERx and Timerx=1 are operating at inter-timer trigger mode. | ||
When Inter-timer Trigger function is enabled, TIMERx is operating at event counting mode to count the input event from Tx pin and TIMERx+1 is operating at external capture trigger-counting mode. | ||
0 = Inter-timer trigger function Disabled. | ||
1 = Inter-timer trigger function Enabled. | ||
Note: In TIMERx+1_CTL, this bit is always 0. | ||
[25] | INTRTGMD | Inter-timer Trigger Mode Selection |
This bit controls the TIMERx (x = 0 or 2) operating behavior when INTRTGEN (TIMERx_CTL[24]) is set to 1. | ||
If INTRTGMD is set to 0 and INTRTGEN (TIMERx_CTL[24]) is set to 1, the TIMERx is operating at event counting mode to count the all input events from Tx pin. | ||
If INTRTGMD and INTRTGEN (TIMERx_CTL[24]) are both set to 1, TIMERx is operating at event counting mode and the number of first incoming events (defined by EVNTDPCNT (TIMERx_ECTL[31:24])) are ignored. | ||
0 = TIMERx count the all input events from Tx pin. | ||
1 = TIMERx ignored the number of first incoming events based on EVNTDPCNT (TIMERx_ECTL[31:24]). | ||
Note: In TIMERx+1_CTL, this bit is always 0. | ||
[28] | TRGPWM | Trigger PWM Enable Bit |
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. | ||
0 = Timer interrupt trigger PWM Disabled. | ||
1 = Timer interrupt trigger PWM Enabled. | ||
Note: If TRGSSEL (TIMERx_CTL[11]) = 0, time-out interrupt signal will trigger PWM. | ||
If TRGSSEL (TIMERx_CTL[11]) = 1, capture interrupt signal will trigger PWM. |
WDT_T::CTL |
[0x0000] Watchdog Timer Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | WTR | Clear Watchdog Timer (Write Protect) |
Please refer to open lock sequence to program it. | ||
Setting this bit will clear the Watchdog timer. | ||
0 = No effect. | ||
1 = Reset the contents of the Watchdog timer. | ||
Note: This bit will be auto cleared after 1 PCLK clock cycle. | ||
[1] | WTRE | Watchdog Timer Reset Function Enable Bit (Write Protect) |
Please refer to open lock sequence to program it. | ||
Setting this bit will enable the Watchdog timer reset function. | ||
0 = Watchdog timer reset function Disabled. | ||
1 = Watchdog timer reset function Enabled. | ||
[2] | WTWKE | Watchdog Timer Wake-up Function Enable Bit (Write Protect) |
Please refer to open lock sequence to program it. | ||
0 = Watchdog timer Wake-up CPU function Disabled. | ||
1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from Power-down mode. | ||
[3] | WTE | Watchdog Timer Enable Bit (Write Protect) |
Please refer to open lock sequence to program it. | ||
0 = Watchdog timer Disabled (this action will reset the internal counter). | ||
1 = Watchdog timer Enabled. | ||
[6:4] | WTIS | Watchdog Timer Interval Selection (Write Protect) |
Please refer to open lock sequence to program it. | ||
The three bits select the time-out interval for the Watchdog timer. This count is free running counter. | ||
Please refer to Table 6.11-1. | ||
[9:8] | WTRDSEL | Watchdog Timer Reset Delay Selection |
When watchdog timeout happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened | ||
Software can select a suitable value of watchdog reset delay period for different watchdog timeout period. | ||
00 = Watchdog reset delay period is 1026 watchdog clock. | ||
01 = Watchdog reset delay period is 130 watchdog clock. | ||
10 = Watchdog reset delay period is 18 watchdog clock. | ||
11 = Watchdog reset delay period is 3 watchdog clock. | ||
Note: This bit will be reset if watchdog reset happened | ||
[31] | DBGEN | WDT Debug Mode Enable Control (Write Protect) |
0 = WDT stopped counting if system is in Debug mode. | ||
1 = WDT still counted even system is in Debug mode. |
WWDT_T::CTL |
[0x0004] Window Watchdog Timer Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | WWDTEN | Window Watchdog Enable Bit |
Set this bit to enable Window Watchdog timer. | ||
0 = Window Watchdog timer function Disabled. | ||
1 = Window Watchdog timer function Enabled. | ||
[11:8] | PERIODSEL | WWDT Pre-scale Period Select |
These three bits select the pre-scale for the WWDT counter period. | ||
Please refer toTable 6.12-1 WWDT Prescaler Value Selection. | ||
[21:16] | WINCMP | WWDT Window Compare Bits |
Set this register to adjust the valid reload window. | ||
Note: WWDTRLD register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal. | ||
[31] | DBGEN | WWDT Debug Enable Bit |
0 = WWDT stopped count if system is in Debug mode. | ||
1 = WWDT still counted even system is in Debug mode. |
SC_T::CTL |
[0x0004] SC Control Register.
Bits | Field | Descriptions |
---|---|---|
[0] | SCEN | SC Engine Enable Bit |
Set this bit to 1 to enable SC operation | ||
If this bit is cleared, SC will force all transition to IDLE state | ||
Note1: SCEN must be set to 1 before filling in other registers, or smart card will not work properly. | ||
Note2: If SCEN is activated, all function can work correctly | ||
If SCEN is not activated, when CPU write data to SMC, only Flip-flop which works in PCLK domain will turn on for two PCLK cycle, Flip-flop working in SCLK domain will not be turn on. | ||
[1] | RXOFF | RX Transition Disable Bit |
0 = The receiver Enabled. | ||
1 = The receiver Disabled. | ||
Note1: If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored. | ||
Note2: After hardware activation and hardware warm reset are done, RXOFF is set to 0 automatically. | ||
[2] | TXOFF | TX Transition Disable Bit |
0 = The transceiver Enabled. | ||
1 = The transceiver Disabled. | ||
[3] | AUTOCEN | Auto Convention Enable Bit |
0 = Auto-convention Disabled. | ||
1 = Auto-convention Enabled | ||
When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11. | ||
If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F | ||
After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically | ||
If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR (if ACERRIEN (SC_INTEN[10]) = 1 to CPU. | ||
[5:4] | CONSEL | Convention Selection |
00 = Direct convention. | ||
01 = Reserved. | ||
10 = Reserved. | ||
11 = Inverse convention. | ||
Note: If AUTOCEN(SC_CTL[3]) is enabled, this field is ignored. | ||
[7:6] | RXTRGLV | Rx Buffer Trigger Level |
When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if [RDAIEN](SC_INTEN[0]) is enabled, an interrupt will be generated). | ||
00 = INTR_RDA Trigger Level with 01 Bytes. | ||
01 = INTR_RDA Trigger Level with 02 Bytes. | ||
10 = INTR_RDA Trigger Level with 03 Bytes. | ||
11 = Reserved. | ||
[12:8] | BGT | Block Guard Time (BGT) |
Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions | ||
This field indicates the counter for the bit length of block guard time | ||
According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it. | ||
Note: The real block guard time is BGT + 1. | ||
[14:13] | TMRSEL | Timer Selection |
00 = All internal timer function Disabled. | ||
11 = Internal 24 bit timer and two 8 bit timers Enabled | ||
Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]. | ||
Other configurations are reserved | ||
[15] | NSB | Stop Bit Length |
This field indicates the length of stop bit. | ||
0 = The stop bit length is 2 ETU. | ||
1= The stop bit length is 1 ETU. | ||
Note: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length. | ||
[18:16] | RXRTY | RX Error Retry Count Number |
This field indicates the maximum number of receiver retries that are allowed when parity error has occurred | ||
Note1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number. | ||
Note2: This field cannot be changed when RX_ERETRY_EN enabled | ||
The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. | ||
[19] | RXRTYEN | RX Error Retry Enable Bit |
This bit enables receiver retry function when parity error has occurred. | ||
0 = RX error retry function Disabled. | ||
1 = RX error retry function Enabled. | ||
Note: Software must fill in the RXRTY value before enabling this bit. | ||
[22:20] | TXRTY | TX Error Retry Count Number |
This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. | ||
Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. | ||
Note2: This field cannot be changed when TXRTYEN enabled | ||
The change flow is to disable TXRTYEN first and then fill in new retry value. | ||
[23] | TXRTYEN | TX Error Retry Enable Bit |
This bit enables transmitter retry function when parity error has occurred. | ||
0 = TX error retry function Disabled. | ||
1 = TX error retry function Enabled. | ||
[25:24] | CDDBSEL | Card Detect De-bounce Selection |
This field indicates the card detect de-bounce selection. | ||
00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks. | ||
Other configurations are reserved. | ||
[30] | SYNC | SYNC Flag Indicator(Read Only) |
Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.SYNC flag is | ||
0 = synchronizing is completion, user can write new data to RXRTY and TXRTY. | ||
1 = Last value is synchronizing. |
I2C_T::CTL |
[0x0000] I2C Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | I2CEN | I2C Function Enable Bit |
0 = I2C function Disabled. | ||
1 = I2C function Enabled. | ||
[1] | AA | Assert Acknowledge Control Bit |
When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when | ||
1.)A slave is acknowledging the address sent from master, | ||
2.) The receiver devices are acknowledging the data sent by transmitter | ||
When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. | ||
[2] | STO | I2C STOP Control Bit |
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected | ||
This bit will be cleared by hardware automatically. | ||
[3] | STA | I2C START Command |
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. | ||
[4] | SI | I2C Status |
When a new state is present in the I2C_STATUS register, if the INTEN bit is set, the I2C interrupt is requested | ||
It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go ahead until the STOP is active or the I2CEN is disabled. | ||
0 = I2C's Status disabled and the I2C protocol function will go ahead. | ||
1 = I2C's Status active. | ||
Note: If software wants to skip clearing INTSTS (I2C_INTSTS[0]), it also can write 1 to SI bit and must set INTEN bit | ||
That INTSTS (I2C_INTSTS[0]) will be cleared when SI is cleared. | ||
[7] | INTEN | Interrupt Enable Bit |
0 = I2C interrupt Disabled. | ||
1 = I2C interrupt Enabled. |
SPI_T::CTL |
[0x0000] SPI Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | GOBUSY | SPI Transfer Control Bit and Busy Status |
0 = Writing this bit 0 will stop data transfer if SPI is transferring. | ||
1 = In Master mode, writing 1 to this bit will start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the slave is ready to communicate with a master. | ||
If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1' | ||
As the transfer is finished, this bit will be cleared automatically | ||
Software can read this bit to check if the SPI is in busy status. | ||
In FIFO mode, this bit will be controlled by hardware | ||
Software should not modify this bit | ||
In slave mode, this bit always returns 1 when software reads this register | ||
In master mode, this bit reflects the busy or idle status of SPI. | ||
Note: | ||
1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. | ||
2 | ||
When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer. | ||
[1] | RXNEG | Receive on Negative Edge |
0 = The received data is latched on the rising edge of SPI_CLK. | ||
1 = The received data is latched on the falling edge of SPI_CLK. | ||
Note: Refer to Edge section. | ||
[2] | TXNEG | Transmit on Negative Edge |
0 = The transmitted data output is changed on the rising edge of SPI_CLK. | ||
1 = The transmitted data output is changed on the falling edge of SPI_CLK. | ||
Note: Refer to Edge section. | ||
[7:3] | DWIDTH | Data Width |
This field specifies how many bits can be transmitted / received in one transaction | ||
The minimum bit length is 8 bits and can be up to 32 bits. | ||
01000 = 8 bits are transmitted in one transaction. | ||
01001 = 9 bits are transmitted in one transaction. | ||
01010 = 10 bits are transmitted in one transaction. | ||
--— | ||
11111 = 31 bits are transmitted in one transaction. | ||
00000 = 32 bits are transmitted in one transaction. | ||
[10] | LSB | Send LSB First |
0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first. | ||
1 = The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (SPI_RX0/1). | ||
Note: Refer to LSB first section. | ||
[11] | CLKPOL | Clock Polarity |
0 = The default level of SPI_CLK is low. | ||
1 = The default level of SPI_CLK is high. | ||
Note: Refer to Clock Parity section. | ||
[15:12] | SUSPITV | Suspend Interval (Master Only) |
These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer | ||
The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL = 0 | ||
If CLKPOL = 1, the interval is from the rising clock edge to the falling clock edge. | ||
The default value is 0x3 | ||
The desired suspend interval is obtained according to the following equation: )(SP_]YCLE[3]0) + 0.5) * period of SPI_CLK | ||
For example, | ||
SUSPITV = 0x0 .... 0.5 SPI_CLK clock cycle. | ||
SUSPITV = 0x1 .... 1.5 SPI_CLK clock cycle. | ||
...... | ||
SUSPITV = 0xE .... 14.5 SPI_CLK clock cycle. | ||
SUSPITV = 0xF .... 15.5 SPI_CLK clock cycle. | ||
[17] | UNITIEN | Unit Transfer Interrupt Enable Bit |
0 = SPI unit transfer interrupt Disabled. | ||
1 = SPI unit transfer interrupt Enabled. | ||
[18] | SLAVE | Slave Mode Selection |
0 = SPI controller set as Master mode. | ||
1 = SPI controller set as Slave mode. | ||
Note: Refer to Slave Selection section | ||
[19] | REORDER | Byte Reorder Function Enable Bit |
0 = Byte reorder function Disabled. | ||
1 = Enable byte reorder function and insert a byte suspend interval among each byte | ||
The setting of DWIDTH must be configured as 00b ( 32 bits/ word) | ||
Note: The suspend interval is defined in SUSPITV. Refer to Byte Reorder section. | ||
Note: Byte Suspend is only used in SPI Byte Reorder mode. | ||
[21] | FIFOM | FIFO Mode Enable Bit |
0 = FIFO mode Disabled (in Normal mode). | ||
1 = FIFO mode Enabled. | ||
Note: Refer to FIFO Mode section. | ||
[22] | TWOBIT | 2-bit Transfer Mode Enable Bit |
0 = 2-bit transfer mode Disabled. | ||
1 = 2-bit transfer mode Enabled. | ||
Refer to Two Bit Transfer Mode section | ||
Note: automatically | ||
[28] | DUALDIR | Dual I/O Mode Direction Control |
0 = Date read in the Dual I/O Mode function. | ||
1 = Data write in the Dual I/O Mode function. | ||
Refer to Dual I/O Mode section. | ||
[29] | DUALIOEN | Dual I/O Mode Enable Bit |
0 = Dual I/O Mode function Disabled. | ||
1 = Dual I/O Mode function Enabled. | ||
Refer to Dual I/O Mode section. | ||
[30] | WKSSEN | Wake-up by Slave Select Enable Bit |
0 = Wake-up function Disabled. | ||
1 = Wake-up function Enabled. | ||
Note: The Slave select wake-up function is only available in SPI Slave mode | ||
When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port | ||
After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. | ||
[31] | WKCLKEN | Wake-up by SPI Clock Enable Bit |
0 = Wake-up function Disabled. | ||
1 = Wake-up function Enabled. | ||
Note: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port | ||
After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. |
ADC_T::CTL |
[0x0048] A/D Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | ADCEN | A/D Converter Enable Bit |
0 = A/D Converter Disabled. | ||
1 = A/D Converter Enabled. | ||
Note: Before starting A/D conversion function, this bit should be set to 1 | ||
Clear it to 0 to disable A/D converter analog circuit to save power consumption. | ||
[1] | ADCIEN | A/D Interrupt Enable Bit |
A/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1. | ||
0 = A/D interrupt function Disabled. | ||
1 = A/D interrupt function Enabled. | ||
[3:2] | ADMD | A/D Converter Operation Mode |
00 = Single conversion. | ||
01 = Reserved. | ||
10 = Single-cycle scan. | ||
11 = Continuous scan. | ||
[5:4] | HWTRGSEL | Hardware Trigger Source Select Bit |
In hardware trigger mode, ADC starts to convert by the external trigger from STADC pin or PWM trigger. | ||
00= A/D conversion is started by external STADC pin. | ||
01= Reserved. | ||
10= Reserved. | ||
11= A/D conversion is started by PWM0 trigger. | ||
Note: Software should disable HWTRGEN (ADC_CTL[8]) and clear SWTRG (ADC_CTL[11]) before change HWTRGSEL (ADC_CTL[5:4]). | ||
[7:6] | HWTRGCOND | Hardware External Trigger Condition |
These two bits decide external pin STADC trigger event is level or edge | ||
The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state. | ||
00 = Low level. | ||
01 = High level. | ||
10 = Falling edge. | ||
11 = Rising edge. | ||
[8] | HWTRGEN | Hardware External Trigger Enable Bit |
Enable or disable triggering of A/D conversion by external STADC pin | ||
If external trigger is enabled, ADC starts to convert by the selected hardware trigger source. | ||
0= External trigger Disabled. | ||
1= External trigger Enabled. | ||
[9] | PTEN | PDMA Transfer Enable Bit |
When A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request. | ||
0 = PDMA data transfer Disabled. | ||
1 = PDMA data transfer in ADC_DATx Enabled. | ||
Note: When PDMA transfer enable, software must set ADCIEN (ADC_CTL[1]) = 0 to disable interrupt | ||
PDMA can access ADC_DATx registers by block or single transfer mode. | ||
[10] | DIFF | Differential Mode Selection |
0 = ADC is operated in single-ended mode. | ||
1 = ADC is operated in differential mode. | ||
Note: Calibration should calibrated each time when switching between single-ended and differential mode. | ||
[11] | SWTRG | Software Trigger A/D Conversion Start |
0 = Conversion stopped and A/D converter enter idle state. | ||
1 = Conversion starts. | ||
ADC can be start to convert from three sources: software write, external pin STADC and PWM trigger | ||
SWTRG (ADC_CTL[11]) is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels | ||
In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset. | ||
Note: After ADC conversion is done, SW needs to wait at least one ADC clock before to set this bit high again. | ||
[13:12] | TMSEL | Select A/D Enable Time-out Source |
Selects one of four timer events source to trigger ADC starts to convert. | ||
00 = TMR0. | ||
01 = TMR1. | ||
10 = TMR2. | ||
11 = TMR3. | ||
[15] | TMTRGMOD | Timer Event Trigger ADC Conversion Mode |
0 = Timer event trigger ADC conversion disabled. | ||
1 = ADC can be start to conversion by timer out event. | ||
Note1: setting TMSEL (ADC_CTL[13:12]) to select timer event from timer0~3. | ||
Note2: If timer event is used as ADC trigger source, ADCEN (ADC_CTL[0]) needs to be disabled. | ||
[17:16] | REFSEL | Reference Voltage Source Selection |
00 = Select as reference voltage. | ||
01 = Select as reference voltage. | ||
10 = Select as reference voltage. | ||
11 = Reserved. | ||
[19:18] | RESSEL | Resolution Selection |
00 = 6-bit. ADC result will put at RESULT (ADC_DATx[5:0]). | ||
01 = 8-bit. ADC result will put at RESULT (ADC_DATx[7:0]). | ||
10 = 10-bit. ADC result will put at RESULT (ADC_DATx[9:0]). | ||
11 = 12-bit. ADC result will put at RESULT (ADC_DATx[11:0]). | ||
[31:24] | TMPDMACNT | Timer Event PDMA Count |
When each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting. | ||
Note: The total amount of PDMA transferring data should be set in PDMA byte count register | ||
When PDMA finish is set, ADC will not be enabled and will start transfer even though the timer event occurred. |
PWM_T::CTL0 |
[0x0000] PWM0 Control Register 0
Bits | Field | Descriptions |
---|---|---|
[5:0] | CTRLDn | Center Re-load |
Each bit n controls the corresponding PWM0 channel n. | ||
In up-down counter type, PERIOD will load to PBUF at the end point of each period | ||
CMPDAT will load to CMPBUF at the center point of a period | ||
[21:16] | IMMLDENn | Immediately Load Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = PERIOD will load to PBUF at the end point of each period | ||
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. | ||
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. | ||
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. | ||
[30] | DBGHALT | ICE Debug Mode Counter Halt (Write Protect) |
If counter halt is enabled, PWM0 all counters will keep current value until exit ICE debug mode. | ||
0 = ICE debug mode counter halt Disabled. | ||
1 = ICE debug mode counter halt Enabled. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[31] | DBGTRIOFF | ICE Debug Mode Acknowledge Disable Bit (Write Protect) |
0 = ICE debug mode acknowledgement effects PWM0 output. | ||
PWM0 pin will be forced as tri-state while ICE debug mode acknowledged. | ||
1 = ICE debug mode acknowledgement disabled. | ||
PWM0 pin will keep output no matter ICE debug mode acknowledged or not. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. |
ACMP_T::CTL0 |
[0x0000] Analog Comparator 0 Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | ACMPEN | Comparator Enable Bit |
0 = Comparator 0 Disabled. | ||
1 = Comparator 0 Enabled. | ||
[1] | ACMPIE | Comparator Interrupt Enable Bit |
0 = Comparator 0 interrupt Disabled. | ||
1 = Comparator 0 interrupt Enabled | ||
If WKEN (ACMP_CTL0[31]) is set to 1, the wake-up interrupt function will be enabled as well. | ||
[2] | HYSEN | Comparator Hysteresis Enable Bit |
0 = Comparator 0 hysteresis Disabled. | ||
1 = Comparator 0 hysteresis Enabled. | ||
[5:4] | NEGSEL | Comparator Negative Input Selection |
00 = ACMP0_N pin. | ||
01 = Internal comparator reference voltage (CRV). | ||
10 = Internal reference voltage (Int_VREF). | ||
11 = AVSS pin. | ||
[31] | WKEN | Power-down Wake-up Enable Bit |
0 = Wake-up function Disabled. | ||
1 = Wake-up function Enabled. |
PWM_T::CTL1 |
[0x0004] PWM0 Control Register 1
Bits | Field | Descriptions |
---|---|---|
[1:0] | CNTTYPE0 | PWM0 Counter Behavior Type 0 |
Each bit n controls corresponding PWM0 channel n. | ||
00 = Up counter type (supports in capture mode). | ||
01 = Down count type (supports in capture mode). | ||
10 = Up-down counter type. | ||
11 = Reserved. | ||
[5:4] | CNTTYPE2 | PWM0 Counter Behavior Type 2 |
Each bit n controls corresponding PWM0 channel n. | ||
00 = Up counter type (supports in capture mode). | ||
01 = Down count type (supports in capture mode). | ||
10 = Up-down counter type. | ||
11 = Reserved. | ||
[9:8] | CNTTYPE4 | PWM0 Counter Behavior Type 4 |
Each bit n controls corresponding PWM0 channel n. | ||
00 = Up counter type (supports in capture mode). | ||
01 = Down count type (supports in capture mode). | ||
10 = Up-down counter type. | ||
11 = Reserved. | ||
[26:24] | PWMMODEn | PWM0 Mode |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = PWM0 independent mode. | ||
1 = PWM0 complementary mode. | ||
Note: When operating in group function, these bits must all set to the same mode. |
I2C_T::CTL2 |
[0x0040] I2C Control Register 2
Bits | Field | Descriptions |
---|---|---|
[0] | WKUPEN | I2C Wake-up Function Enable Bit |
0 = I2C wake-up function Disabled. | ||
1 = I2C wake-up function Enabled. | ||
[1] | OVIEN | I2C Overrun Interrupt Control Bit |
0 = Overrun event interrupt Disabled. | ||
1 = Send a interrupt to system when the TWOLVBUF bit is enabled and there is overrun event in received buffer. | ||
[2] | URIEN | I2C Under run Interrupt Control Bit |
0 = Under run event interrupt Disabled. | ||
1 = Send a interrupt to system when the TWOLVBUF bit is enabled and there is under-run event happened in transmitted buffer. | ||
[4] | TWOLVBUF | Two Level Buffer Enable Bit |
0 = Two level buffer Disabled. | ||
1 = Two level buffer Enabled. | ||
[5] | NOSTRETCH | I2C BuS Stretch |
0 = The I2C SCL bus is stretched by hardware if the SI (I2C_CTL[4]) is not cleared. | ||
1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared. | ||
[6] | DATMODE | Data Mode Enable Bit |
0 = Data mode Disabled. | ||
1 = Data mode Enabled. | ||
[7] | MSDAT | Master or Slave in Data Mode Enable Control |
0 = Master writes data to device. | ||
1 = Slave reads data from device. |
PDMA_CH_T::CTLn |
[0x0000] PDMA channel n Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | CHEN | PDMA Channel Enable Bit |
Setting this bit to 1 enables PDMA operation | ||
If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. | ||
Note: SWRST (PDMA_CTLn[1], n= 1~4) will clear this bit. | ||
[1] | SWRST | Software Engine Reset |
0 = No effect. | ||
1 = Reset the internal state machine, pointers and internal buffer | ||
The contents of all control registers will not be cleared | ||
This bit will be automatically cleared after few clock cycles. | ||
[5:4] | SASEL | Transfer Source Address Direction Selection |
00 = Transfer Source address is incremented successively. | ||
01 = Reserved. | ||
10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations). | ||
11 = Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically | ||
PDMA will start another transfer without user trigger until CHEN disabled | ||
When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address). | ||
[7:6] | DASEL | Transfer Destination Address Direction Selection |
00 = Transfer Destination address is incremented successively. | ||
01 = Reserved. | ||
10 = Transfer Destination address is fixed | ||
(This feature can be used when data transferred from multiple sources to a single destination). | ||
11 = Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically | ||
PDMA will start another transfer without user trigger until CHEN disabled | ||
When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address). | ||
[12] | TOUTEN | Time-out Enable Bit |
This bit will enable PDMA Time-out counter (PDMA_TOCn, n=1~4) | ||
While this counter counts to 0, the TOUTIF (PDMA_INTSTSn[6], n=1~4) will be set. | ||
0 = PDMA internal counter Disabled. | ||
1 = PDMA internal counter Enabled. | ||
[20:19] | TXWIDTH | Transfer Width Selection |
This field is used for transfer width. | ||
00 = One word (32-bit) is transferred for every PDMA operation. | ||
01 = One byte (8-bit) is transferred for every PDMA operation. | ||
10 = One half-word (16-bit) is transferred for every PDMA operation. | ||
11 = Reserved. | ||
[23] | TRIGEN | Trigger Enable Bit |
0 = No effect. | ||
1 = PDMA data transfer Enabled. | ||
Note1: When PDMA transfer completed, this bit will be cleared automatically. | ||
Note2: If the bus error occurs, all PDMA transfer will be stopped | ||
User must reset all PDMA channels, and then trigger again. |
UART_T::CTRL |
[0x0004] UART Control Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RXRST | RX Field Software Reset |
When RXRST (UART_CTL[0]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. | ||
0 = No effect. | ||
1 = Reset the RX internal state machine and pointers. | ||
Note: This bit will automatically clear at least 3 UART peripheral clock cycles. | ||
[1] | TXRST | TX Field Software Reset |
When TXRST (UART_CTL[1]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. | ||
0 = No effect. | ||
1 = Reset the TX internal state machine and pointers. | ||
Note: This bit will automatically clear at least 3 UART peripheral clock cycles | ||
[2] | RXOFF | Receiver Disable Bit |
0 = Receiver Enabled. | ||
1 = Receiver Disabled. | ||
Note1: In RS-485 NMM mode, user can set this bit to receive data before detecting address byte. | ||
Note2: In RS-485 AAD mode, this bit will be setting to 1 automatically. | ||
Note3: In RS-485 AUD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit. | ||
[3] | TXOFF | Transfer Disable Bit |
0 = Transfer Enabled. | ||
1 = Transfer Disabled. | ||
[4] | ATORTSEN | nRTS Auto-flow Control Enable Bit |
0 = nRTS auto-flow control Disabled. | ||
1 = nRTS auto-flow control Enabled. | ||
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_TLCTL[13:12]), the UART will de-assert nRTS signal. | ||
[5] | ATOCTSEN | nCTS Auto-flow Control Enable Bit |
0 = nCTS auto-flow control Disabled. | ||
1 = nCTS auto-flow control Enabled. | ||
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). | ||
[6] | RXDMAEN | RX DMA Enable Bit |
This bit can enable or disable RX DMA service. | ||
0 = RX DMA Disabled. | ||
1 = RX DMA Enabled. | ||
[7] | TXDMAEN | TX DMA Enable Bit |
This bit can enable or disable TX DMA service. | ||
0 = TX DMA Disabled. | ||
1 = TX DMA Enabled. | ||
[8] | FTOEN | Frame Time Out Enable Bit |
This bit is used to enable the timer counter even the FIFO is still empty. | ||
0 = Frame time out Disabled. | ||
1 = Frame time out Enabled. | ||
[12] | ABRDEN | Auto-baud Rate Detect Enable Bit |
0 = Auto-baud rate detect function Disabled. | ||
1 = Auto-baud rate detect function Enabled. | ||
Note: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_IER [7]) be enabled). | ||
[14:13] | ABRDBITS | Auto-baud Rate Detect Bit Length |
00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. | ||
01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. | ||
10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. | ||
11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. | ||
Note: The calculation of bit number includes the START bit. |
PDMA_CH_T::DAn |
DMA_CRC_T::DAT |
[0x0080] CRC Write Data Register
Bits | Field | Descriptions |
---|---|---|
[31:0] | DATA | CRC Write Data Bits |
When operating in CPU mode, user can write data to this field to perform CRC operation. | ||
When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written by user. | ||
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register are only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register are only DATA[15:0] bits. |
UART_T::DAT |
[0x0000] UART Receive/Transmit Buffer Register
Bits | Field | Descriptions |
---|---|---|
[7:0] | DAT | Receive /Transmit Buffer |
Write Operation: | ||
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT. | ||
Read Operation: | ||
By reading this register, the UART will return an 8-bit data received from receiving FIFO. |
SC_T::DAT |
[0x0000] SC Receive/Transmit Holding Buffer Register.
Bits | Field | Descriptions |
---|---|---|
[7:0] | DAT | Receive/Transmit Holding Buffer |
Write Operation: | ||
By writing data to DAT, the SC will send out an 8-bit data. | ||
Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed. | ||
Read Operation: | ||
By reading DAT, the SC will return an 8-bit received data. |
I2C_T::DAT |
ADC_T::DAT |
[0x0000] A/D Data Register 0 ~ 17
Bits | Field | Descriptions |
---|---|---|
[11:0] | RESULT | A/D Conversion Result |
This field contains conversion result of ADC. | ||
[16] | VALID | Valid Flag |
This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read. | ||
0 = Data in RESULT (ADC_DAT[11:0]) bits is not valid. | ||
1 = Data in RESULT (ADC_DAT[11:0]) bits is valid. | ||
[17] | OV | over Run Flag |
If converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register, OV is set to 1 | ||
It is cleared by hardware after the ADC_DATx register is read. | ||
0 = Data in RESULT (ADC_DAT[11:0]) is recent conversion result. | ||
1 = Data in RESULT (ADC_DAT[11:0]) overwrote. |
GPIO_T::DATMSK |
[0x000c] Pn Data Output Write Mask
Bits | Field | Descriptions |
---|---|---|
[0] | DMASK0 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | DMASK1 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | DMASK2 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | DMASK3 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | DMASK4 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | DMASK5 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | DMASK6 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | DMASK7 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | DMASK8 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | DMASK9 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | DMASK10 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | DMASK11 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | DMASK12 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | DMASK13 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | DMASK14 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | DMASK15 | Port A-f Pin[N] Data Output Write Mask |
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
If the write signal is masked, writing data to the protect bit is ignored. | ||
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
Note2: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note3: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
GP_DB_T::DBCTL |
[0x0180] Interrupt De-bounce Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | DBCLKSEL | De-bounce Sampling Cycle Selection |
0000 = Sample interrupt input once per 1 clocks. | ||
0001 = Sample interrupt input once per 2 clocks. | ||
0010 = Sample interrupt input once per 4 clocks. | ||
0011 = Sample interrupt input once per 8 clocks. | ||
0100 = Sample interrupt input once per 16 clocks. | ||
0101 = Sample interrupt input once per 32 clocks. | ||
0110 = Sample interrupt input once per 64 clocks. | ||
0111 = Sample interrupt input once per 128 clocks. | ||
1000 = Sample interrupt input once per 256 clocks. | ||
1001 = Sample interrupt input once per 2*256 clocks. | ||
1010 = Sample interrupt input once per 4*256 clocks. | ||
1011 = Sample interrupt input once per 8*256 clocks. | ||
1100 = Sample interrupt input once per 16*256 clocks. | ||
1101 = Sample interrupt input once per 32*256 clocks. | ||
1110 = Sample interrupt input once per 64*256 clocks. | ||
1111 = Sample interrupt input once per 128*256 clocks. | ||
[4] | DBCLKSRC | De-bounce Counter Clock Source Selection |
0 = De-bounce counter clock source is the HCLK. | ||
1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). | ||
[5] | ICLKON | Interrupt Clock on Mode |
0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. | ||
1 = All I/O pins edge detection circuit is always active after reset. | ||
Note: It is recommended to disable this bit to save system power if no special application concern. |
GPIO_T::DBEN |
[0x0014] Pn De-Bounce Enable Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | DBEN0 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | DBEN1 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | DBEN2 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | DBEN3 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | DBEN4 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | DBEN5 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | DBEN6 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | DBEN7 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | DBEN8 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | DBEN9 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | DBEN10 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | DBEN11 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | DBEN12 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | DBEN13 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | DBEN14 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | DBEN15 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
0 = Px.n de-bounce function Disabled. | ||
1 = Px.n de-bounce function Enabled. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
FMC_T::DFBA |
[0x0014] Data Flash Base Address
Bits | Field | Descriptions |
---|---|---|
[31:0] | DFBA | Data Flash Base Address |
This register indicates Data Flash start address. It is a read only register. | ||
The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1. | ||
This register is valid when DFEN (CONFIG0[0]) =0 . |
GPIO_T::DINOFF |
[0x0004] Pn Digital Input Path Disable Control
Bits | Field | Descriptions |
---|---|---|
[16] | DINOFF0 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[17] | DINOFF1 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[18] | DINOFF2 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[19] | DINOFF3 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[20] | DINOFF4 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[21] | DINOFF5 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[22] | DINOFF6 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[23] | DINOFF7 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[24] | DINOFF8 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[25] | DINOFF9 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[26] | DINOFF10 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[27] | DINOFF11 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[28] | DINOFF12 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[29] | DINOFF13 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[30] | DINOFF14 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[31] | DINOFF15 | Port A-f Pin[N] Digital Input Path Disable Bit |
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
0 = Px.n digital input path Enabled. | ||
1 = Px.n digital input path Disabled (digital input tied to low). | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
DMA_CRC_T::DMABCNT |
DMA_CRC_T::DMACBCNT |
[0x001c] CRC DMA Current Transfer Byte Count Register
Bits | Field | Descriptions |
---|---|---|
[15:0] | CBCNT | CRC DMA Current Remained Byte Count (Read Only) |
This field indicates the current remained byte count of CRC DMA. | ||
Note: Setting the CRCRST (CRC_CTL[1]) bit to 1 will clear this register value. |
DMA_CRC_T::DMACSA |
DMA_CRC_T::DMAINTEN |
[0x0020] CRC DMA Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | TABTIEN | CRC DMA Read/Write Target Abort Interrupt Enable Bit |
Enable this bit will generate the CRC DMA Target Abort interrupt signal while TABTIF (CRC_DMAINTSTS[0]) bit is set to 1. | ||
0 = Target abort interrupt Disabled during CRC DMA transfer. | ||
1 = Target abort interrupt Enabled during CRC DMA transfer. | ||
[1] | TDIEN | CRC DMA Block Transfer Done Interrupt Enable Bit |
Enable this bit will generate the CRC DMA Transfer Done interrupt signal while TDIF (CRC_DMAINTSTS[1]) bit is set to 1. | ||
0 = Interrupt Disabled when CRC DMA transfer done. | ||
1 = Interrupt Enabled when CRC DMA transfer done. |
DMA_CRC_T::DMAISTS |
[0x0024] CRC DMA Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | TABTIF | CRC DMA Read/Write Target Abort Interrupt Flag |
This bit indicates that CRC bus has error or not during CRC DMA transfer. | ||
0 = No bus error response received during CRC DMA transfer. | ||
1 = Bus error response received during CRC DMA transfer. | ||
Note1: This bit is cleared by writing 1 to it. | ||
Note2: This bit indicates bus master received error response or not | ||
If bus master received error response, it means that CRC transfer target abort is happened | ||
DMA will stop transfer and respond this event to user then CRC state machine goes to IDLE state | ||
When target abort occurred, user must reset DMA before transfer those data again. | ||
[1] | TDIF | CRC DMA Transfer Done Interrupt Flag |
This bit indicates that CRC DMA transfer has finished or not. | ||
0 = Not finished if TRIGEN (CRC_CTL[23]) has enabled. | ||
1 = CRC transfer done if TRIGEN (CRC_CTL[23]) has enabled. | ||
Note1: This bit is cleared by writing 1 to it. | ||
Note2: When CRC DMA transfer is done, TRIGEN (CRC_CTL[23]) will be cleared automatically. |
DMA_CRC_T::DMASA |
GPIO_T::DOUT |
[0x0008] Pn Data Output Value
Bits | Field | Descriptions |
---|---|---|
[0] | DOUT0 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | DOUT1 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | DOUT2 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | DOUT3 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | DOUT4 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | DOUT5 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | DOUT6 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | DOUT7 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | DOUT8 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | DOUT9 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | DOUT10 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | DOUT11 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | DOUT12 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | DOUT13 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | DOUT14 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | DOUT15 | Port A-f Pin[N] Output Value |
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
PWM_T::DTCTL0_1 |
[0x0070] PWM0 Dead-Time Control Register 0_1
Bits | Field | Descriptions |
---|---|---|
[11:0] | DTCNT | Dead-time Counter (Write Protect) |
The dead-time can be calculated from the following formula: | ||
Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) |
Dead-time insertion is only active when this PWM0 pair complementary mode is enabled | ||
If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
0 = Dead-time insertion Disabled on the pin pair. | ||
1 = Dead-time insertion Enabled on the pin pair. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[24] | DTCKSEL | Dead-time Clock Select (Write Protect) |
0 = Dead-time clock source from PWM0_CLKn. | ||
1 = Dead-time clock source from prescaler output. | ||
Note: This register is write protected. Refer to REGWRPROT register. |
PWM_T::DTCTL2_3 |
[0x0074] PWM0 Dead-Time Control Register 2_3
Bits | Field | Descriptions |
---|---|---|
[11:0] | DTCNT | Dead-time Counter (Write Protect) |
The dead-time can be calculated from the following formula: | ||
Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) |
Dead-time insertion is only active when this PWM0 pair complementary mode is enabled | ||
If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
0 = Dead-time insertion Disabled on the pin pair. | ||
1 = Dead-time insertion Enabled on the pin pair. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[24] | DTCKSEL | Dead-time Clock Select (Write Protect) |
0 = Dead-time clock source from PWM0_CLKn. | ||
1 = Dead-time clock source from prescaler output. | ||
Note: This register is write protected. Refer to REGWRPROT register. |
PWM_T::DTCTL4_5 |
[0x0078] PWM0 Dead-Time Control Register 4_5
Bits | Field | Descriptions |
---|---|---|
[11:0] | DTCNT | Dead-time Counter (Write Protect) |
The dead-time can be calculated from the following formula: | ||
Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) |
Dead-time insertion is only active when this PWM0 pair complementary mode is enabled | ||
If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
0 = Dead-time insertion Disabled on the pin pair. | ||
1 = Dead-time insertion Enabled on the pin pair. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[24] | DTCKSEL | Dead-time Clock Select (Write Protect) |
0 = Dead-time clock source from PWM0_CLKn. | ||
1 = Dead-time clock source from prescaler output. | ||
Note: This register is write protected. Refer to REGWRPROT register. |
TIMER_T::ECTL |
[0x0020] Timer Extended Control Register
Bits | Field | Descriptions |
---|---|---|
[31:24] | EVNTDPCNT | Event Drop Count |
This field indicates timer how many events dropped after inter-timer trigger function enable. | ||
For example, if user configured EVNTDPCNT to 7, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event. | ||
Note: ECNTDPCNT only takes effect when INTRTGEN (TIMERx_CTL[24]) INTRTGMD (TIMERx_CTL[25]) are both set to 1. |
SC_T::EGT |
SC_T::ETUCTL |
[0x0014] SC Element Time Unit Control Register.
Bits | Field | Descriptions |
---|---|---|
[11:0] | ETURDIV | ETU Rate Divider |
The field indicates the clock rate divider. | ||
The real ETU is ETURDIV + 1. | ||
Note: Software can configure this field, but this field must be greater than 0x004. |
ADC_T::EXTSMPT0 |
[0x0070] A/D Sampling Time Counter Register 0
Bits | Field | Descriptions |
---|---|---|
[3:0] | EXTSMPT_CH0 | Additional ADC Sample Clock for Channel 0 |
If the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal | ||
The default sampling time is 1 ADC clocks | ||
The additional clock number will be inserted to lengthen the sampling clock. | ||
0 = Number of additional clock cycles is 0. | ||
1 = Number of additional clock cycles is 1. | ||
2 = Number of additional clock cycles is 2. | ||
3 = Number of additional clock cycles is 4. | ||
4 = Number of additional clock cycles is 8. | ||
5 = Number of additional clock cycles is 16. | ||
6 = Number of additional clock cycles is 32. | ||
7 = Number of additional clock cycles is 64. | ||
8 = Number of additional clock cycles is 128. | ||
9 = Number of additional clock cycles is 256. | ||
10 = Number of additional clock cycles is 512. | ||
11 = Number of additional clock cycles is 1024. | ||
12 = Number of additional clock cycles is 1024. | ||
13 = Number of additional clock cycles is 1024. | ||
14 = Number of additional clock cycles is 1024. | ||
15 = Number of additional clock cycles is 1024. | ||
[7:4] | EXTSMPT_CH1 | Additional ADC Sample Clock for Channel 1 |
The same as channel 0 description. | ||
[11:8] | EXTSMPT_CH2 | Additional ADC Sample Clock for Channel 2 |
The same as channel 0 description. | ||
[15:12] | EXTSMPT_CH3 | Additional ADC Sample Clock for Channel 3 |
The same as channel 0 description. | ||
[19:16] | EXTSMPT_CH4 | Additional ADC Sample Clock for Channel 4 |
The same as channel 0 description. | ||
[23:20] | EXTSMPT_CH5 | Additional ADC Sample Clock for Channel 5 |
The same as channel 0 description. | ||
[27:24] | EXTSMPT_CH6 | Additional ADC Sample Clock for Channel 6 |
The same as channel 0 description. | ||
[31:28] | EXTSMPT_CH7 | Additional ADC Sample Clock for Channel 7 |
The same as channel 0 description. |
ADC_T::EXTSMPT1 |
PWM_T::FAILBRK |
[0x00c4] PWM0 System Fail Brake Control Register
Bits | Field | Descriptions |
---|---|---|
[1] | BODBRKEN | Brown-out Detection Trigger PWM0 Brake Function 0 Enable Bit |
0 = Brake Function triggered by BOD Disabled. | ||
1 = Brake Function triggered by BOD Enabled. | ||
[3] | CORBRKEN | Core Lockup Detection Trigger PWM0 Brake Function 0 Enable Bit |
0 = Brake Function triggered by Core lockup detection Disabled. | ||
1 = Brake Function triggered by Core lockup detection Enabled. |
PWM_T::FCAPDAT0 |
PWM_T::FCAPDAT1 |
PWM_T::FCAPDAT2 |
PWM_T::FCAPDAT3 |
PWM_T::FCAPDAT4 |
PWM_T::FCAPDAT5 |
SPI_T::FIFOCTL |
[0x003c] SPI FIFO Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | RXFBCLR | Receive FIFO Buffer Clear |
0 = No clear the received FIFO. | ||
1 = Clear the received FIFO. | ||
Note: This bit is used to clear the receiver counter in FIFO Mode | ||
This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter | ||
After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1. | ||
[1] | TXFBCLR | Transmit FIFO Buffer Clear |
0 = Not clear the transmitted FIFO. | ||
1 = Clear the transmitted FIFO. | ||
Note: This bit is used to clear the transmit counter in FIFO Mode | ||
This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter | ||
After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1. | ||
[2] | RXTHIEN | Receive Threshold Interrupt Enable Bit |
0 = RX threshold interrupt Disabled. | ||
1 = RX threshold interrupt Enabled. | ||
[3] | TXTHIEN | Transmit Threshold Interrupt Enable Bit |
0 = TX threshold interrupt Disabled. | ||
1 = TX threshold interrupt Enabled. | ||
[4] | RXOVIEN | Receive FIFO over Run Interrupt Enable Bit |
0 = RX FIFO over run interrupt Disabled. | ||
1 = RX FIFO over run interrupt Enabled. | ||
[7] | RXTOIEN | RX Read Time Out Interrupt Enable Bit |
0 = RX read Timeout Interrupt Disabled. | ||
1 = RX read Timeout Interrupt Enabled. | ||
[26:24] | RXTH | Received FIFO Threshold |
If RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8]) will be set to 1. | ||
[30:28] | TXTH | Transmit FIFO Threshold |
If TX valid data counts are smaller than or equal to TXTH, TXTHIF (SPI_STATUS[10]) will be set to 1. |
UART_T::FIFOSTS |
[0x0018] UART FIFO Status Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RXOVIF | RX Overflow Error Status Flag (Read Only) |
This bit is set when RX FIFO overflow | ||
If the number of bytes of received data is greater than RX_FIFO (UART_RBR) size, this bit will be set. | ||
0 = RX FIFO is not overflow. | ||
1 = RX FIFO is overflow. | ||
Note: This bit is read only, but can be cleared by writing 1 to it. | ||
[1] | RXEMPTY | Receiver FIFO Empty (Read Only) |
This bit initiate RX FIFO empty or not. | ||
0 = RX FIFO is not empty. | ||
1 = RX FIFO is empty. | ||
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high | ||
It will be cleared when UART receives any new data. | ||
[2] | RXFULL | Receiver FIFO Full (Read Only) |
This bit initiates RX FIFO full or not. | ||
0 = RX FIFO is not full. | ||
1 = RX FIFO is full. | ||
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
[4] | PEF | Parity Error State Status Flag (Read Only) |
This bit is set to logic 1 whenever the received character does not have a valid parity bit. | ||
0 = No parity error is generated. | ||
1 = Parity error is generated. | ||
Note: This bit is read only, but can be cleared by writing '1' to it. | ||
[5] | FEF | Framing Error Flag (Read Only) |
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). | ||
0 = No framing error is generated. | ||
1 = Framing error is generated. | ||
Note: This bit is read only, but can be cleared by writing '1' to it. | ||
[6] | BIF | Break Interrupt Flag( Read Only) |
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). | ||
0 = No Break interrupt is generated. | ||
1 = Break interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing '1' to it. | ||
[8] | TXOVIF | TX Overflow Error Interrupt Status Flag (Read Only) |
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. | ||
0 = TX FIFO did not overflow. | ||
1 = TX FIFO overflowed. | ||
Note: This bit is read only, but can be cleared by writing 1 to it. | ||
[9] | TXEMPTY | Transmitter FIFO Empty (Read Only) |
This bit indicates TX FIFO empty or not. | ||
0 = TX FIFO is not empty. | ||
1 = TX FIFO is empty. | ||
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high | ||
It will be cleared when writing data into DAT (TX FIFO not empty). | ||
[10] | TXFULL | Transmitter FIFO Full (Read Only) |
This bit indicates TX FIFO full or not. | ||
0 = TX FIFO is not full. | ||
1 = TX FIFO is full. | ||
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
[11] | TXENDF | Transmitter Empty Flag (Read Only) |
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. | ||
0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. | ||
1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. | ||
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. | ||
[20:16] | RXPTR | RX FIFO Pointer (Read Only) |
This field indicates the RX FIFO Buffer Pointer | ||
When UART receives one byte from external device, RXPTR increases one | ||
When one byte of RX FIFO is read by CPU, RXPTR decreases one. | ||
The Maximum value shown in RXPTR is 15 | ||
When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 | ||
As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 | ||
[28:24] | TXPTR | TX-fIFO Pointer (Read Only) |
This field indicates the TX FIFO Buffer Pointer | ||
When CPU writes one byte into UART_DAT, TXPTR increases one | ||
When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. | ||
The Maximum value shown in TXPTR is 15 | ||
When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 | ||
As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 |
RTC_T::FREQADJ |
FMC_T::FTCTL |
[0x0018] Flash Access Time Control Register
Bits | Field | Descriptions |
---|---|---|
[6:4] | FOM | Frequency Optimization Mode (Write Protect) |
The Nano103 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency. | ||
001 = Frequency <= 20MHz. | ||
100 = Frequency <= 36MHz. (default power-on setting) | ||
Others = Reserved | ||
Note:This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[7] | CACHEOFF | Flash Cache Disable Control (Write Protect) |
0 = Flash Cache function Enabled (default). | ||
1 = Flash Cache function Disabled. | ||
Note:This bit is write protected. Refer to the SYS_REGLCTL register. |
UART_T::FUNCSEL |
DMA_GCR_T::GCTL |
[0x0000] PDMA Global Control Register
Bits | Field | Descriptions |
---|---|---|
[9] | CKEN1 | PDMA Controller Channel 1 Clock Enable Bit |
0 = PDMA channel 1 clock Disabled. | ||
1 = PDMA channel 1 clock Enabled. | ||
[10] | CKEN2 | PDMA Controller Channel 2 Clock Enable Bit |
0 = PDMA channel 2 clock Disabled. | ||
1 = PDMA channel 2 clock Enabled. | ||
[11] | CKEN3 | PDMA Controller Channel 3 Clock Enable Bit |
0 = PDMA channel 3 clock Disabled. | ||
1 = PDMA channel 3 clock Enabled. | ||
[12] | CKEN4 | PDMA Controller Channel 4 Clock Enable Bit |
0 = PDMA channel 4 clock Disabled. | ||
1 = PDMA channel 4 clock Enabled. | ||
[24] | CKENCRC | CRC Controller Clock Enable Bit |
0 = CRC channel clock Disabled. | ||
1 = CRC channel clock Enabled. |
DMA_GCR_T::GINTSTS |
[0x000c] PDMA Global Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[1] | IF1 | PDMA Channel 1 Interrupt Status (Read Only) |
This bit indicates the interrupt status of PDMA channel 1. | ||
[2] | IF2 | PDMA Channel 2 Interrupt Status Flag of (Read Only) |
This bit indicates the interrupt status of PDMA channel 2. | ||
[3] | IF3 | PDMA Channel 3 Interrupt Status (Read Only) |
This bit indicates the interrupt status of PDMA channel 3. | ||
[4] | IF4 | PDMA Channel 4 Interrupt Status Flag (Read Only) |
This bit indicates the interrupt status of PDMA channel 4. | ||
[16] | IFCRC | CRC Controller Interrupt Status Flag (Read Only) |
This bit indicates the interrupt status of CRC controller |
SYS_T::GPA_MFPH |
[0x0034] GPIOA High Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | PA8MFP | PA.8 Multi-function Pin Selection |
0000 = GPIOA[8] | ||
0001 = I2C0 data input/output pin. | ||
0010 = Timer0 external counter input. | ||
0011 = SmartCard0 clock pin. | ||
0100 = SPI2 slave select pin. | ||
0101 = Timer0 toggle output. | ||
0110 = UART0 Clear to Send input pin. | ||
[7:4] | PA9MFP | PA.9 Multi-function Pin Selection |
0000 = GPIOA[9] | ||
0001 = I2C0 clock pin. | ||
0010 = Timer1 external counter input. | ||
0011 = SmartCard0 data pin. | ||
0100 = SPI0 serial clock pin. | ||
0101 = Timer1 toggle output. | ||
0110 = UART1 Request to Send output pin. | ||
0111 = Snooper pin. | ||
[11:8] | PA10MFP | PA.10 Multi-function Pin Selection |
0000 = GPIOA[10] | ||
0001 = I2C1 data input/output pin. | ||
0010 = Timer2 external counter input. | ||
0011 = SmartCard0 power pin. | ||
0100 = SPI2 1st MISO (Master In, Slave Out) pin. | ||
0101 = Timer2 toggle output. | ||
[15:12] | PA11MFP | PA.11 Multi-function Pin Selection |
0000 = GPIOA[11] | ||
0001 = I2C1 clock pin. | ||
0010 = Timer3 external counter input. | ||
0011 = SmartCard0 reset pin. | ||
0100 = SPI2 1st MOSI (Master Out, Slave In) pin. | ||
0101 = Timer3 toggle output. | ||
[19:16] | PA12MFP | PA.12 Multi-function Pin Selection |
0000 = GPIOA[12] | ||
0001 = PWM0 channel0 output/capture input. | ||
0011 = Timer0 capture input. | ||
0101 = I2C0 data input/output pin. | ||
[23:20] | PA13MFP | PA.13 Multi-function Pin Selection |
0000 = GPIOA[13] | ||
0001 = PWM0 channel1 output/capture input. | ||
0011 = Timer1 capture input. | ||
0101 = I2C0 clock pin. | ||
[27:24] | PA14MFP | PA.14 Multi-function Pin Selection |
0000 = GPIOA[14] | ||
0001 = PWM0 channel2 output/capture input. | ||
0010 = I2C1 data input/output pin. | ||
0011 = I2C1 data input/output pin. | ||
0101 = Timer2 external counter input. | ||
0110 = Data receiver input pin for UART0. | ||
0111 = Timer2 toggle output. | ||
[31:28] | PA15MFP | PA.15 Multi-function Pin Selection |
0000 = GPIOA[15] | ||
0001 = PWM0 channel3 output/capture input. | ||
0010 = I2C1 clock pin. | ||
0011 = Timer1 capture input. | ||
0100 = SmartCard0 power pin. | ||
0110 = Data transmitter output pin for UART0. | ||
0111 = Timer3 toggle output. |
SYS_T::GPA_MFPL |
[0x0030] GPIOA Low Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | PA0MFP | PA.0 Multi-function Pin Selection |
0000 = GPIOA[0] | ||
0001 = ADC analog input0. | ||
0010 = Comparator1 P-end input. | ||
0011 = Timer0 capture input. | ||
0101 = PWM0 channel2 output/capture input. | ||
[7:4] | PA1MFP | PA.1 Multi-function Pin Selection |
0000 = GPIOA[1] | ||
0001 = ADC analog input1. | ||
0010 = Comparator1 N-end input. | ||
0110 = SPI0 2nd MISO (Master In, Slave Out) pin. | ||
[11:8] | PA2MFP | PA.2 Multi-function Pin Selection |
0000 = GPIOA[2] | ||
0001 = ADC analog input2. | ||
0101 = Data receiver input pin for UART1. | ||
[15:12] | PA3MFP | PA.3 Multi-function Pin Selection |
0000 = GPIOA[3] | ||
0001 = ADC analog input3. | ||
0101 = Data transmitter output pin for UART1. | ||
0110 = SPI3 1st MOSI (Master Out, Slave In) pin. | ||
[19:16] | PA4MFP | PA.4 Multi-function Pin Selection |
0000 = GPIOA[4] | ||
0001 = ADC analog input4. | ||
0101 = I2C0 data input/output pin. | ||
0110 = SPI3 1st MISO (Master In, Slave Out) pin. | ||
[23:20] | PA5MFP | PA.5 Multi-function Pin Selection |
0000 = GPIOA[5] | ||
0001 = ADC analog input5. | ||
0101 = I2C0 clock pin. | ||
0110 = SPI3 serial clock pin. | ||
[27:24] | PA6MFP | PA.6 Multi-function Pin Selection |
0000 = GPIOA[6] | ||
0001 = ADC analog input6. | ||
0010 = Comparator1 output. | ||
0011 = Timer3 capture input. | ||
0100 = Timer3 external counter input. | ||
0101 = PWM0 channel3 output/capture input. | ||
0111 = Timer3 toggle output. |
SYS_T::GPB_MFPH |
[0x003c] GPIOB High Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | PB8MFP | PB.8 Multi-function Pin Selection |
0000 = GPIOB[8] | ||
0001 = ADC external trigger input. | ||
0010 = Timer0 external counter input. | ||
0011 = External interrupt0 input pin. | ||
0100 = Timer0 toggle output. | ||
0111 = Snooper pin. | ||
[7:4] | PB9MFP | PB.9 Multi-function Pin Selection |
0000 = GPIOB[9] | ||
0001 = SPI1 slave select pin. | ||
0010 = Timer2 external counter input. | ||
0100 = Timer2 toggle output. | ||
0101 = External interrupt0 input pin. | ||
[11:8] | PB10MFP | PB.10 Multi-function Pin Selection |
0000 = GPIOB[10] | ||
0001 = SPI0 1st MOSI (Master Out, Slave In) pin. | ||
0100 = Timer2 toggle output. | ||
0101 = SPI0 slave select pin. | ||
[15:12] | PB11MFP | PB.11 Multi-function Pin Selection |
0000 = GPIOB[11] | ||
0001 = PWM0 channel4 output/capture input. | ||
0010= Timer3 external counter input. | ||
0100 = Timer3 toggle output. | ||
0101 = SPI0 1st MISO (Master In, Slave Out) pin. | ||
[23:20] | PB13MFP | PB.13 Multi-function Pin Selection |
0000 = GPIOB[13] | ||
0011 = SPI2 2nd MISO (Master In, Slave Out) pin. | ||
0111 = Snooper pin. | ||
[27:24] | PB14MFP | PB.14 Multi-function Pin Selection |
0000 = GPIOB[14] | ||
0001 = External interrupt0 input pin. | ||
0011 = SPI2 2nd MOSI (Master Out, Slave In) pin. | ||
0100 = SPI2 slave select pin. | ||
[31:28] | PB15MFP | PB.15 Multi-function Pin Selection |
0000 = GPIOB[15] | ||
0001 = External interrupt1 input pin. | ||
0011 = Snooper pin. | ||
0100 = SmartCard1 card detect pin. |
SYS_T::GPB_MFPL |
[0x0038] GPIOB Low Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | PB0MFP | PB.0 Multi-function Pin Selection |
0000 = GPIOB[0] | ||
0001 = Data receiver input pin for UART0. | ||
0011 = SPI1 1st MOSI (Master Out, Slave In) pin. | ||
[7:4] | PB1MFP | PB.1 Multi-function Pin Selection |
0000 = GPIOB[1] | ||
0001 = Data transmitter output pin for UART0. | ||
0011 = SPI1 1st MISO (Master In, Slave Out) pin. | ||
[11:8] | PB2MFP | PB.2 Multi-function Pin Selection |
0000 = GPIOB[2] | ||
0001 = UART0 Request to Send output pin. | ||
0011 = SPI1 serial clock pin. | ||
0100 = Frequency Divider output pin. | ||
[15:12] | PB3MFP | PB.3 Multi-function Pin Selection |
0000 = GPIOB[3] | ||
0001 = UART0 Clear to Send input pin. | ||
0011 = SPI1 slave select pin. | ||
0100 = SmartCard1 card detect pin. | ||
[19:16] | PB4MFP | PB.4 Multi-function Pin Selection |
0000 = GPIOB[4] | ||
0001 = Data receiver input pin for UART1. | ||
0011 = SmartCard0 card detect pin. | ||
0100 = SPI2 slave select pin. | ||
0110 = RTC 1Hz output. | ||
[23:20] | PB5MFP | PB.5 Multi-function Pin Selection |
0000 = GPIOB[5] | ||
0001 = Data transmitter output pin for UART1. | ||
0011 = SmartCard0 reset pin. | ||
0100 = SPI2 serial clock pin. | ||
[27:24] | PB6MFP | PB.6 Multi-function Pin Selection |
0000 = GPIOB[6] | ||
0001 = UART1 Request to Send output pin. | ||
0100 = SPI2 1st MISO (Master In, Slave Out) pin. | ||
[31:28] | PB7MFP | PB.7 Multi-function Pin Selection |
0000 = GPIOB[7] | ||
0001 = UART1 Clear to Send input pin. |
SYS_T::GPC_MFPH |
[0x0044] GPIOC High Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | PC8MFP | PC.8 Multi-function Pin Selection |
0000 = GPIOC[8] | ||
0001 = SPI1 slave select pin. | ||
0101 = I2C1 data input/output pin. | ||
[7:4] | PC9MFP | PC.9 Multi-function Pin Selection |
0000 = GPIOC[9] | ||
0001 = SPI1 serial clock pin. | ||
0101 = I2C1 clock pin. | ||
[11:8] | PC10MFP | PC.10 Multi-function Pin Selection |
0000 = GPIOC[10] | ||
0001 = SPI0 1st MISO (Master In, Slave Out) pin. | ||
0101 = Data receiver input pin for UART1. | ||
[15:12] | PC11MFP | PC.11 Multi-function Pin Selection |
0000 = GPIOC[11] | ||
0001 = SPI1 1st MOSI (Master Out, Slave In) pin. | ||
0101 = Data transmitter output pin for UART1. | ||
[27:24] | PC14MFP | PC.14 Multi-function Pin Selection |
0000 = GPIOC[14] | ||
0001 = UART0 Clear to Send input pin. | ||
[31:28] | PC15MFP | PC.15 Multi-function Pin Selection |
0000 = GPIOC[15] | ||
0001 = UART1 Request to Send output pin. | ||
0011 = Timer0 capture input. |
SYS_T::GPC_MFPL |
[0x0040] GPIOC Low Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | PC0MFP | PC.0 Multi-function Pin Selection |
0000 = GPIOC[0] | ||
0001 = SPI0 slave select pin. | ||
0100 = SmartCard1 clock pin. | ||
0101 = PWM0 break1 input 1. | ||
[7:4] | PC1MFP | PC.1 Multi-function Pin Selection |
0000 = GPIOC[1] | ||
0001 = SPI0 serial clock pin. | ||
0100 = SmartCard1 data pin. | ||
0101 = PWM0 break1 input 0. | ||
[11:8] | PC2MFP | PC.2 Multi-function Pin Selection |
0000 = GPIOC[2] | ||
0001 = SPI0 1st MISO (Master In, Slave Out) pin. | ||
0100 = SmartCard1 power pin. | ||
0101 = PWM0 break0 input 1. | ||
[15:12] | PC3MFP | PC.3 Multi-function Pin Selection |
0000 = GPIOC[3] | ||
0001 = SPI0 1st MOSI (Master Out, Slave In) pin. | ||
0100 = SmartCard1 reset pin. | ||
0101 = PWM0 break0 input 0. | ||
[27:24] | PC6MFP | PC.6 Pin Function Selection |
0000 = GPIOC[6] | ||
0001 = Data receiver input pin for UART1. | ||
0011 = Timer0 capture input. | ||
0100 = SmartCard1 card detect pin. | ||
0101 = PWM0 channel0 output/capture input. | ||
[31:28] | PC7MFP | PC.7 Multi-function Pin Selection |
0000 = GPIOC[7] | ||
0001 = Data transmitter output pin for UART1. | ||
0010 = ADC analog input7. | ||
0011 = Timer1 capture input. | ||
0101 = PWM0 channel1 output/capture input. |
SYS_T::GPD_MFPH |
[0x004c] GPIOD High Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[27:24] | PD14MFP | PD.14 Multi-function Pin Selection |
0000 = GPIOD[14] | ||
0001 = SPI0 2nd MOSI (Master Out, Slave In) pin. | ||
[30:28] | PD15MFP | PD.15 Multi-function Pin Selection |
0000 = GPIOD[15] | ||
0001 = SPI0 2nd MISO (Master In, Slave Out) pin. | ||
0100 = SmartCard1 clock pin. |
SYS_T::GPD_MFPL |
[0x0048] GPIOD Low Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[27:24] | PD6MFP | PD.6 Multi-function Pin Selection |
0000 = GPIOD[6] | ||
0011 = SPI1 2nd MOSI (Master Out, Slave In) pin. | ||
0100 = SmartCard1 reset pin. | ||
[31:28] | PD7MFP | PD.7 Multi-function Pin Selection |
0000 = GPIOD[7] | ||
0011 = SPI1 2nd MISO (Master In, Slave Out) pin. | ||
0100 = SmartCard1 power pin. |
SYS_T::GPE_MFPL |
SYS_T::GPF_MFPL |
[0x0058] GPIOF Low Byte Multiple Function Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | PF0MFP | PF.0 Multi-function Pin Selection |
0000 = GPIOF[1] | ||
0101 = External interrupt0 input pin. | ||
X111 = Serial wired debugger data pin | ||
[7:4] | PF1MFP | PF.1 Multi-function Pin Selection |
0000 = GPIOF[1] | ||
0100 = Frequency Divider output pin. | ||
0101 = External interrupt1 input pin. | ||
X111 = Serial wired debugger clock pin. | ||
[11:8] | PF2MFP | PF.2 Multi-function Pin Selection |
0000 = GPIOF[2] | ||
X111 = External 4~36 MHz (high speed) crystal output pin. | ||
[15:12] | PF3MFP | PF.3 Multi-function Pin Selection |
0000 = GPIOF[3] | ||
X111 = External 4~36 MHz (high speed) crystal input pin. | ||
[27:24] | PF6MFP | PF.6 Multi-function Pin Selection |
0000 = GPIOF[6] | ||
0001 = I2C1 data input/output pin. | ||
X111 = External 32.768 kHz crystal output pin(default). | ||
[31:28] | PF7MFP | PF.7 Multi-function Pin Selection |
0000 = GPIOF[7] | ||
0001 = I2C1 clock pin. | ||
0011 = SmartCard0 card detect pin. | ||
X111 = External 32.768 kHz crystal input pin(default). |
RTC_T::INIT |
[0x0000] RTC Initiation Register
Bits | Field | Descriptions |
---|---|---|
[0] | INIT_ACTIVE | RTC Active Status (Read Only) |
0 = RTC is at reset state. | ||
1 = RTC is at normal active state. | ||
[31:1] | INIT | RTC Initiation |
When RTC block is powered on, RTC is at reset state | ||
User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state | ||
Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. | ||
The INIT is a write-only field and read value will be always 0. |
GPIO_T::INTEN |
[0x001c] Pn Interrupt Enable Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | FLIEN0 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | FLIEN1 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | FLIEN2 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | FLIEN3 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | FLIEN4 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | FLIEN5 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | FLIEN6 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | FLIEN7 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | FLIEN8 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | FLIEN9 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | FLIEN10 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | FLIEN11 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | FLIEN12 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | FLIEN13 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | FLIEN14 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | FLIEN15 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
0 = Px.n level low or high to low interrupt Disabled. | ||
1 = Px.n level low or high to low interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[16] | RHIEN0 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[17] | RHIEN1 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[18] | RHIEN2 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[19] | RHIEN3 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[20] | RHIEN4 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[21] | RHIEN5 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[22] | RHIEN6 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[23] | RHIEN7 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[24] | RHIEN8 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[25] | RHIEN9 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[26] | RHIEN10 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[27] | RHIEN11 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[28] | RHIEN12 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[29] | RHIEN13 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[30] | RHIEN14 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[31] | RHIEN15 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
Set bit to 1 also enable the pin wake-up function. | ||
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
0 = Px.n level high or low to high interrupt Disabled. | ||
1 = Px.n level high or low to high interrupt Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
TIMER_T::INTEN |
[0x000c] Timer Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | CNTIEN | Timer Interrupt Enable Bit |
0 = Timer Interrupt Disabled. | ||
1 = Timer Interrupt Enabled. | ||
Note: If this bit is enabled, when the timer interrupt flag CNTIF (TIMERx_INTSTS[0]) is set to 1, the timer interrupt signal is generated and informed to CPU. | ||
[1] | CAPIEN | Timer External Capture Interrupt Enable Bit |
0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled. | ||
1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled. | ||
Note: CAPIEN is used to enable timer external interrupt | ||
If CAPIEN is enabled, the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1. |
WDT_T::INTEN |
WWDT_T::INTEN |
[0x0008] Window Watchdog Timer Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | WWDTIE | WWDT Interrupt Enable Bit |
Setting this bit will enable the Window Watchdog timer interrupt function. | ||
0 = Watchdog timer interrupt function Disabled. | ||
1 = Watchdog timer interrupt function Enabled. |
RTC_T::INTEN |
[0x0028] RTC Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | ALMIEN | Alarm Interrupt Enable Bit |
0 = RTC Alarm interrupt Disabled. | ||
1 = RTC Alarm interrupt Enabled. | ||
[1] | TICKIEN | Time Tick Interrupt Enable Bit |
0 = RTC Time Tick interrupt Disabled. | ||
1 = RTC Time Tick interrupt Enabled. | ||
[2] | SNPDIEN | Snoop Detection Interrupt Enable Bit |
0 = Snoop detected interrupt Disabled. | ||
1 = Snoop detected interrupt Enabled. |
UART_T::INTEN |
[0x000c] UART Interrupt Enable Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RDAIEN | Receive Data Available Interrupt Enable Bit |
0 = Receive data available interrupt Disabled. | ||
1 = Receive data available interrupt Enabled. | ||
[1] | THREIEN | Transmit Holding Register Empty Interrupt Enable Bit |
0 = Transmit holding register empty interrupt Disabled. | ||
1 = Transmit holding register empty interrupt Enabled. | ||
[2] | RLSIEN | Receive Line Status Interrupt Enable Bit |
0 = Receive Line Status interrupt Disabled. | ||
1 = Receive Line Status interrupt Enabled. | ||
[3] | MODEMIEN | Modem Status Interrupt Enable Bit |
0 = Modem status interrupt Disabled. | ||
1 = Modem status interrupt Enabled. | ||
[4] | RXTOIEN | RX Time-out Interrupt Enable Bit |
0 = RX time-out interrupt Disabled. | ||
1 = RX time-out interrupt Enabled. | ||
[5] | BUFERRIEN | Buffer Error Interrupt Enable Bit |
0 = Buffer error interrupt Disabled. | ||
1 = Buffer error interrupt Enabled. | ||
[6] | WKUPIEN | Wake-up Interrupt Enable Bit |
0 = Wake-up system function Disabled. | ||
1 = Wake-up system function Enabled, when the system is in Power-down mode, one of the wake-up event will wake-up system from Power-down mode. | ||
Note: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and system clock work stable | ||
[7] | ABRIEN | Auto-baud Rate Interrupt Enable Bit |
0 = Auto-baud rate interrupt Disabled. | ||
1 = Auto-baud rate interrupt Enabled. | ||
[8] | LINIEN | LIN Bus Interrupt Enable Bit |
0 = LIN bus interrupt Disabled. | ||
1 = LIN bus interrupt Enabled. | ||
Note: This bit is used for LIN function mode. | ||
[9] | TXENDIEN | Transmitter Empty Interrupt Enable Bit |
0 = Transmit Empty interrupt Disabled. | ||
1 = Transmit Empty interrupt Enabled. | ||
Note: If the bit is enabled, there is interrupt event when the TXENDF (UART_FSR[11]) is activated. |
SC_T::INTEN |
[0x0018] SC Interrupt Enable Control Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RDAIEN | Receive Data Reach Interrupt Enable Bit |
This field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt. | ||
0 = Receive data reach trigger level interrupt Disabled. | ||
1 = Receive data reach trigger level interrupt Enabled. | ||
[1] | TBEIEN | Transmit Buffer Empty Interrupt Enable Bit |
This field is used to enable transmit buffer empty interrupt. | ||
0 = Transmit buffer empty interrupt Disabled. | ||
1 = Transmit buffer empty interrupt Enabled. | ||
[2] | TERRIEN | Transfer Error Interrupt Enable Bit |
This field is used to enable transfer error interrupt | ||
The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]). | ||
0 = Transfer error interrupt Disabled. | ||
1 = Transfer error interrupt Enabled. | ||
[3] | TMR0IEN | Timer0 Interrupt Enable Bit |
This field is used to enable TMR0 interrupt. | ||
0 = Timer0 interrupt Disabled. | ||
1 = Timer0 interrupt Enabled. | ||
[4] | TMR1IEN | Timer1 Interrupt Enable Bit |
This field is used to enable the TMR1 interrupt. | ||
0 = Timer1 interrupt Disabled. | ||
1 = Timer1 interrupt Enabled. | ||
[5] | TMR2IEN | Timer2 Interrupt Enable Bit |
This field is used to enable TMR2 interrupt. | ||
0 = Timer2 interrupt Disabled. | ||
1 = Timer2 interrupt Enabled. | ||
[6] | BGTIEN | Block Guard Time Interrupt Enable Bit |
This field is used to enable block guard time interrupt. | ||
0 = Block guard time Disabled. | ||
1 = Block guard time Enabled. | ||
[7] | CDIEN | Card Detect Interrupt Enable Bit |
This field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12]) | ||
0 = Card detect interrupt Disabled. | ||
1 = Card detect interrupt Enabled. | ||
[8] | INITIEN | Initial End Interrupt Enable Bit |
This field is used to enable activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt. | ||
0 = Initial end interrupt Disabled. | ||
1 = Initial end interrupt Enabled. | ||
[9] | RXTOIEN | Receiver Buffer Time-out Interrupt Enable Bit |
This field is used to enable receiver buffer time-out interrupt. | ||
0 = Receiver buffer time-out interrupt Disabled. | ||
1 = Receiver buffer time-out interrupt Enabled. | ||
[10] | ACERRIEN | Auto Convention Error Interrupt Enable Bit |
This field is used to enable auto-convention error interrupt. | ||
0 = Auto-convention error interrupt Disabled. | ||
1 = Auto-convention error interrupt Enabled. |
PWM_T::INTEN0 |
[0x00e0] PWM0 Interrupt Enable Register 0
Bits | Field | Descriptions |
---|---|---|
[0] | ZIEN0 | PWM0 Zero Point Interrupt Enable Bit 0 |
0 = PWM0 counter0_1 zero point interrupt Disabled. | ||
1 = PWM0 counter0_1 zero point interrupt Enabled. | ||
Note: Odd channels will read always 0 at complementary mode. | ||
[2] | ZIEN2 | PWM0 Zero Point Interrupt Enable Bit 2 |
0 = PWM0 counter2_3 zero point interrupt Disabled. | ||
1 = PWM0 counter2_3 zero point interrupt Enabled. | ||
Note: Odd channels will read always 0 at complementary mode. | ||
[4] | ZIEN4 | PWM0 Zero Point Interrupt Enable Bit 4 |
0 = PWM0 counter4_5 zero point interrupt Disabled. | ||
1 = PWM0 counter4_5 zero point interrupt Enabled. | ||
Note: Odd channels will read always 0 at complementary mode. | ||
[8] | PIEN0 | PWM0 Period Point Interrupt Enable Bit 0 |
0 = PWM0 counter0_1 period point interrupt Disabled. | ||
1 = PWM0 counter0_1 period point interrupt Enabled. | ||
Note: When operating in up-down counter type, period point means center point. | ||
[10] | PIEN2 | PWM0 Period Point Interrupt Enable Bit 2 |
0 = PWM0 counter2_3 period point interrupt Disabled. | ||
1 = PWM0 counter2_3 period point interrupt Enabled. | ||
Note: When operating in up-down counter type, period point means center point. | ||
[12] | PIEN4 | PWM0 Period Point Interrupt Enable Bit 4 |
0 = PWM0 counter4_5 period point interrupt Disabled. | ||
1 = PWM0 counter4_5 period point interrupt Enabled. | ||
Note: When operating in up-down counter type, period point means center point. | ||
[21:16] | CMPUIENn | PWM0 Compare Up Count Interrupt Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Compare up count interrupt Disabled. | ||
1 = Compare up count interrupt Enabled. | ||
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. | ||
[29:24] | CMPDIENn | PWM0 Compare Down Count Interrupt Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Compare down count interrupt Disabled. | ||
1 = Compare down count interrupt Enabled. | ||
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
PWM_T::INTEN1 |
[0x00e4] PWM0 Interrupt Enable Register 1
Bits | Field | Descriptions |
---|---|---|
[0] | BRKEIEN0_1 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect) |
0 = Edge-detect Brake interrupt for channel0/1 Disabled. | ||
1 = Edge-detect Brake interrupt for channel0/1 Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[1] | BRKEIEN2_3 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect) |
0 = Edge-detect Brake interrupt for channel2/3 Disabled. | ||
1 = Edge-detect Brake interrupt for channel2/3 Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[2] | BRKEIEN4_5 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect) |
0 = Edge-detect Brake interrupt for channel4/5 Disabled. | ||
1 = Edge-detect Brake interrupt for channel4/5 Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[8] | BRKLIEN0_1 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect) |
0 = Level-detect Brake interrupt for channel0/1 Disabled. | ||
1 = Level-detect Brake interrupt for channel0/1 Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[9] | BRKLIEN2_3 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect) |
0 = Level-detect Brake interrupt for channel2/3 Disabled. | ||
1 = Level-detect Brake interrupt for channel2/3 Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[10] | BRKLIEN4_5 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect) |
0 = Level-detect Brake interrupt for channel4/5 Disabled. | ||
1 = Level-detect Brake interrupt for channel4/5 Enabled. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. |
PDMA_CH_T::INTENn |
[0x0020] PDMA channel n Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[0] | TABTIEN | PDMA Read/Write Target Abort Interrupt Enable Bit |
0 = Target abort interrupt Disabled during PDMA transfer. | ||
1 = Target abort interrupt Enabled during PDMA transfer. | ||
[1] | TDIEN | PDMA Transfer Done Interrupt Enable Bit |
0 = Interrupt Disabled when PDMA transfer is done. | ||
1 = Interrupt Enabled when PDMA transfer is done. | ||
[6] | TOUTIEN | Time-out Interrupt Enable Bit |
0 = Time-out interrupt Disabled. | ||
1 = Time-out interrupt Enabled. | ||
[8] | PCNTIEN | Periodic Count Interrupt Enable Bit |
This field indicates how many data transferred to generate interrupt periodically. | ||
0 = Periodic transfer count interrupt Disabled. | ||
1 = Periodic transfer count interrupt Enabled. |
GPIO_T::INTSRC |
[0x0020] Pn Interrupt Source Flag
Bits | Field | Descriptions |
---|---|---|
[0] | INTSRC0 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | INTSRC1 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | INTSRC2 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | INTSRC3 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | INTSRC4 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | INTSRC5 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | INTSRC6 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | INTSRC7 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | INTSRC8 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | INTSRC9 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | INTSRC10 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | INTSRC11 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | INTSRC12 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | INTSRC13 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | INTSRC14 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | INTSRC15 | Port A-f Pin[N] Interrupt Source Flag |
Write Operation : | ||
0 = No action. | ||
1 = Clear the corresponding pending interrupt. | ||
Read Operation : | ||
0 = No interrupt at Px.n. | ||
1 = Px.n generates an interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
GPIO_T::INTSTS |
[0x0028] Pn Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | FLISTS0 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | FLISTS1 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | FLISTS2 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | FLISTS3 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | FLISTS4 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | FLISTS5 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | FLISTS6 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | FLISTS7 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | FLISTS8 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | FLISTS9 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | FLISTS10 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | FLISTS11 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | FLISTS12 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | FLISTS13 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | FLISTS14 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | FLISTS15 | Port A-f Pin[N] Falling Edge Interrupt Status |
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No falling edge interrupt at Px.n. | ||
1 = Px.n generates an falling edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[16] | RHISTS0 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[17] | RHISTS1 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[18] | RHISTS2 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[19] | RHISTS3 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[20] | RHISTS4 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[21] | RHISTS5 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[22] | RHISTS6 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[23] | RHISTS7 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[24] | RHISTS8 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[25] | RHISTS9 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[26] | RHISTS10 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[27] | RHISTS11 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[28] | RHISTS12 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[29] | RHISTS13 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[30] | RHISTS14 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[31] | RHISTS15 | Port A-f Pin[N] Rising Edge Interrupt Status |
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
0 = No rising edge interrupt at Px.n. | ||
1 = Px.n generates an rising edge interrupt. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
TIMER_T::INTSTS |
[0x0010] Timer Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | CNTIF | Timer Interrupt Status |
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. | ||
0 = No effect. | ||
1 = CNT (TIMERx_CNT[23:0]) value matches the CMPDAT (TIMERx_CMP[23:0]) value. | ||
Note: This bit is cleared by writing 1 to it. | ||
[1] | CAPIF | Timer External Capture Interrupt Flag |
This bit indicates the timer external capture interrupt flag status. | ||
0 = Tx_EXT (x= 0~3) pin interrupt did not occur. | ||
1 = Tx_EXT (x= 0~3) pin interrupt occurred. | ||
Note1: This bit is cleared by writing 1 to it. | ||
Note2: When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, this bit will set to 1 by hardware. | ||
Note3: If a new incoming capture event detected before CPU clearing the CAPIF status, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. | ||
[4] | TWKF | Timer Wake-up Flag |
This bit indicates the interrupt wake-up flag status of timer. | ||
0 = Timer does not cause CPU wake-up. | ||
1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. | ||
Note: This bit is cleared by writing 1 to it. | ||
[5] | CAPDATOF | Capture Data Overflow Flag |
This status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status. | ||
If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. | ||
0 = New incoming capture event didnu2019t detect before CPU clearing CAPIF (TIMERx_INTSTS[1]) status. | ||
1 = New incoming capture event detected before CPU clearing CAPIF (TIMERx_INTSTS[1]) status. | ||
Note: This bit is cleared by writing 1 to it. | ||
[6] | CAPFEDF | Capture Falling Edge Detected Flag |
This flag indicates the edge detected on Tx_EXT pin is rising edge or falling edge. | ||
0 = Rising edge detected on Tx_EXT pin. | ||
1 = Falling edge detected on Tx_EXT pin. | ||
Note1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value. | ||
Note2: When a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status, Timer will keep this bit unchanged. |
RTC_T::INTSTS |
[0x002c] RTC Interrupt Indicator Register
Bits | Field | Descriptions |
---|---|---|
[0] | ALMIF | RTC Alarm Interrupt Flag |
When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1 | ||
Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode. | ||
0 = Alarm condition is not matched. | ||
1 = Alarm condition is matched. | ||
Note: Write 1 to clear this bit. | ||
[1] | TICKIF | RTC Time Tick Interrupt Flag |
When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1 | ||
Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode. | ||
0 = Tick condition does not occur. | ||
1 = Tick condition occur. | ||
Note: Write 1 to clear to clear this bit. | ||
[2] | SNPDIF | Snoop Detect Interrupt Flag |
When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1 | ||
Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled. | ||
0 = No snoop event is detected. | ||
1 = Snoop event is detected. | ||
Note: Write 1 to clear this bit. |
UART_T::INTSTS |
[0x0010] UART Interrupt Status Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RDAIF | Receive Data Available Interrupt Flag (Read Only) |
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_ISR[0]) will be set | ||
If RDAIEN (UART_IER [0]) is enabled, the RDA interrupt will be generated. | ||
0 = No RDA interrupt flag is generated. | ||
1 = RDA interrupt flag is generated. | ||
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_TLCTL[9:8]) | ||
[1] | THREIF | Transmit Holding Register Empty Interrupt Flag (Read Only) |
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register | ||
If THREIEN (UART_IER[1]) is enabled, the THRE interrupt will be generated. | ||
0 = No THRE interrupt flag is generated. | ||
1 = THRE interrupt flag is generated. | ||
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty) | ||
[2] | RLSIF | Receive Line Interrupt Flag (Read Only) |
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FSR[6]), FEF(UART_FSR[5]) and PEF(UART_FSR[4]), is set) | ||
If RLSIEN (UART_IER [2]) is enabled, the RLS interrupt will be generated. | ||
0 = No RLS interrupt flag is generated. | ||
1 = RLS interrupt flag is generated. | ||
Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit" | ||
At the same time, the bit of ADDRDETF (UART_TRSR[0]) is also set. | ||
Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FSR[6]), FEF(UART_FSR[5]) and PEF(UART_FSR[4]) are cleared. | ||
Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FSR[6]) , FEF(UART_FSR[5]) and PEF(UART_FSR[4]) and ADDRDETF (UART_TRSR[0]) are cleared. | ||
[3] | MODEMIF | MODEM Interrupt Flag (Read Only) Channel |
This bit is set when the nCTS pin has state change (CTSDETF (UART_MCSR[18]) = 1) | ||
If MODEMIEN (UART_IER [3]) is enabled, the Modem interrupt will be generated. | ||
0 = No Modem interrupt flag is generated. | ||
1 = Modem interrupt flag is generated. | ||
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MCSR[18]). | ||
[4] | RXTOIF | Rime-out Interrupt Flag (Read Only) |
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC | ||
If RXTOIEN (UART_IER [4]) is enabled, the Tout interrupt will be generated. | ||
0 = No Time-out interrupt flag is generated. | ||
1 = Time-out interrupt flag is generated. | ||
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it | ||
[5] | BUFERRIF | Buffer Error Interrupt Flag (Read Only) |
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FSR[8]) or RXOVIF (UART_FSR[0]) is set) | ||
When BUFERRIF (UART_ISR[5])is set, the transfer is not correct | ||
If BFERRIEN (UART_IER [5]) is enabled, the buffer error interrupt will be generated. | ||
0 = No buffer error interrupt flag is generated. | ||
1 = Buffer error interrupt flag is generated. | ||
Note: This bit is read only | ||
This bit is cleared if both of RXOVIF(UART_FSR[0]) and TXOVIF(UART_FSR[8]) are cleared to 0 by writing 1 to RXOVIF(UART_FSR[0]) and TXOVIF(UART_FSR[8]). | ||
[6] | WKUPIF | Wake-up Interrupt Flag (Read Only) |
This bit is set if chip wake-up from power-down state by one of UART controller wake-up event. | ||
0 = Chip stays in power-down state. | ||
1 = Chip wake-up from power-down state by one of UART controller wake-up event. | ||
Note1: If WKDATEN (UART_IER[6]) is enabled, the wake-up interrupt is generated. | ||
Note2: This bit is read only, but can be cleared by writing '1' to one of UART_WKUPSTS[4:0] (THRTOWKSTS or THRWKSTS or CTSWKSTS or DATWKSTS or ADRWKSTS). | ||
[7] | ABRIF | Auto-baud Rate Interrupt Status Flag (Read Only) |
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_IER[7]) is set then the auto-baud rate interrupt will be generated. | ||
0 = No Auto-Baud Rate interrupt is generated. | ||
1 = Auto-Baud Rate interrupt is generated. | ||
Note1: This bit is read only, but can be cleared by writing 1 to ABRDTOIF (UART_TRSR[2]) or ABRDIF (UART_TRSR[1]). | ||
Note2: This bit is cleared when both the ABRDTOIF and ABRDIF are cleared. | ||
[8] | LINIF | LIN Interrupt Status Flag (Read Only) |
This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LINIEN(UART_IER[8]) is set then the LIN interrupt will be generated. | ||
0 = No LIN interrupt is generated. | ||
1 = LIN interrupt is generated. | ||
Note1: This bit is read only, but can be cleared by it by writing 1 to BITEF (UART_TRSR[5]), LINTXIF (UART_TRSR[3]) or LINRXIF (UART_TRSR[4]). | ||
Note2: This bit is cleared when both the BITEF, LINTXIF and LINRXIF are cleared. |
SC_T::INTSTS |
[0x001c] SC Interrupt Status Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RDAIF | Receive Data Reach Interrupt Status Flag (Read Only) |
This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. | ||
Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]) | ||
If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically. | ||
[1] | TBEIF | Transmit Buffer Empty Interrupt Status Flag (Read Only) |
This field is used for transmit buffer empty interrupt status flag. | ||
Note: This field is the status flag of transmit buffer empty state | ||
If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically. | ||
[2] | TERRIF | Transfer Error Interrupt Status Flag (Read Only) |
This field is used for transfer error interrupt status flag | ||
The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30]). | ||
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]) | ||
So, if software wants to clear this bit, software must write 1 to each field. | ||
[3] | TMR0IF | Timer0 Interrupt Status Flag (Read Only) |
This field is used for TMR0 interrupt status flag. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
[4] | TMR1IF | Timer1 Interrupt Status Flag (Read Only) |
This field is used for TMR1 interrupt status flag. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
[5] | TMR2IF | Timer2 Interrupt Status Flag (Read Only) |
This field is used for TMR2 interrupt status flag. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
[6] | BGTIF | Block Guard Time Interrupt Status Flag (Read Only) |
This field is used for block guard time interrupt status flag. | ||
Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled. | ||
Note2: This bit is read only, but it can be cleared by writing u201C1u201D to it. | ||
[7] | CDIF | Card Detect Interrupt Status Flag (Read Only) |
This field is used for card detect interrupt status flag | ||
The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]). | ||
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])] | ||
So if software wants to clear these bits, software must write 1 to these field. | ||
[8] | INITIF | Initial End Interrupt Status Flag (Read Only) |
This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
[9] | RXTOIF | Receiver Buffer Time-out Interrupt Status Flag (Read Only) |
This field is used for receiver buffer time-out interrupt status flag. | ||
Note: This field is the status flag of receiver buffer time-out state | ||
If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer, | ||
[10] | ACERRIF | Auto Convention Error Interrupt Status Flag (Read Only) |
This field indicates auto convention sequence error | ||
If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. |
I2C_T::INTSTS |
[0x0004] I2C Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | INTSTS | I2C STATUS's Interrupt Status |
When a new I2C state is present in the I2C_STATUS register, the INTSTS flag is set by hardware | ||
If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.This bit must be cleared by software writing 1 . | ||
Note: If software wants to skip clearing INTSTS, it can also write 1 to SI (I2C_CTL [4]) bit and must set INTEN (I2C_CTL [7]) bit | ||
INISTS will be cleared when SI is cleared. | ||
[1] | TOIF | Time-out Status |
0 = No Time-out flag. | ||
1 = Time-out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set. | ||
Note: This bit can be cleared by writing 1 to it. | ||
[7] | WKAKDONE | Wake-up Address Frame Acknowledge Bit Done |
0 = The ACK bit cycle of address match frame is not done. | ||
1 = The ACK bit cycle of address match frame is done in power-down. | ||
Note: This bit can be cleared by writing 1 to it. |
PWM_T::INTSTS0 |
[0x00e8] PWM0 Interrupt Flag Register 0
Bits | Field | Descriptions |
---|---|---|
[0] | ZIF0 | PWM0 Zero Point Interrupt Flag 0 |
This bit is set by hardware when PWM0_CH0 counter reaches zero, software can write 1 to clear this bit to zero. | ||
[2] | ZIF2 | PWM0 Zero Point Interrupt Flag 2 |
This bit is set by hardware when PWM0_CH2 counter reaches zero, software can write 1 to clear this bit to zero. | ||
[4] | ZIF4 | PWM0 Zero Point Interrupt Flag 4 |
This bit is set by hardware when PWM0_CH4 counter reaches zero, software can write 1 to clear this bit to zero. | ||
[8] | PIF0 | PWM0 Period Point Interrupt Flag 0 |
This bit is set by hardware when PWM0_CH0 counter reaches PWM0_PERIOD0, software can write 1 to clear this bit to zero. | ||
[10] | PIF2 | PWM0 Period Point Interrupt Flag 2 |
This bit is set by hardware when PWM0_CH2 counter reaches PWM0_PERIOD2, software can write 1 to clear this bit to zero. | ||
[12] | PIF4 | PWM0 Period Point Interrupt Flag 4 |
This bit is set by hardware when PWM0_CH4 counter reaches PWM0_PERIOD4, software can write 1 to clear this bit to zero. | ||
[21:16] | CMPUIFn | PWM0 Compare Up Count Interrupt Flag |
Flag is set by hardware when PWM0 counter up count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it | ||
Each bit n controls the corresponding PWM0 channel n. | ||
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. | ||
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. | ||
[29:24] | CMPDIFn | PWM0 Compare Down Count Interrupt Flag |
Each bit n controls the corresponding PWM0 channel n. | ||
Flag is set by hardware when PWM0 counter down count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it. | ||
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. | ||
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
PWM_T::INTSTS1 |
[0x00ec] PWM0 Interrupt Flag Register 1
Bits | Field | Descriptions |
---|---|---|
[0] | BRKEIF0 | PWM0 Channel0 Edge-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel0 edge-detect brake event do not happened. | ||
1 = When PWM0 channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[1] | BRKEIF1 | PWM0 Channel1 Edge-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel1 edge-detect brake event do not happened. | ||
1 = When PWM0 channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[2] | BRKEIF2 | PWM0 Channel2 Edge-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel2 edge-detect brake event do not happened. | ||
1 = When PWM0 channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[3] | BRKEIF3 | PWM0 Channel3 Edge-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel3 edge-detect brake event do not happened. | ||
1 = When PWM0 channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[4] | BRKEIF4 | PWM0 Channel4 Edge-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel4 edge-detect brake event do not happened. | ||
1 = When PWM0 channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[5] | BRKEIF5 | PWM0 Channel5 Edge-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel5 edge-detect brake event do not happened. | ||
1 = When PWM0 channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[8] | BRKLIF0 | PWM0 Channel0 Level-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel0 level-detect brake event do not happened. | ||
1 = When PWM0 channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[9] | BRKLIF1 | PWM0 Channel1 Level-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel1 level-detect brake event do not happened. | ||
1 = When PWM0 channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[10] | BRKLIF2 | PWM0 Channel2 Level-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel2 level-detect brake event do not happened. | ||
1 = When PWM0 channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[11] | BRKLIF3 | PWM0 Channel3 Level-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel3 level-detect brake event do not happened. | ||
1 = When PWM0 channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[12] | BRKLIF4 | PWM0 Channel4 Level-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel4 level-detect brake event do not happened. | ||
1 = When PWM0 channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[13] | BRKLIF5 | PWM0 Channel5 Level-detect Brake Interrupt Flag (Write Protect) |
0 = PWM0 channel5 level-detect brake event do not happened. | ||
1 = When PWM0 channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
[16] | BRKESTS0 | PWM0 Channel0 Edge-detect Brake Status (Read Only) |
0 = PWM0 channel0 edge-detect brake state is released. | ||
1 = When PWM0 channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel0 at brake state, writing 1 to clear. | ||
[17] | BRKESTS1 | PWM0 Channel1 Edge-detect Brake Status (Read Only) |
0 = PWM0 channel1 edge-detect brake state is released. | ||
1 = When PWM0 channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel1 at brake state, writing 1 to clear. | ||
[18] | BRKESTS2 | PWM0 Channel2 Edge-detect Brake Status (Read Only) |
0 = PWM0 channel2 edge-detect brake state is released. | ||
1 = When PWM0 channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel2 at brake state, writing 1 to clear. | ||
[19] | BRKESTS3 | PWM0 Channel3 Edge-detect Brake Status (Read Only) |
0 = PWM0 channel3 edge-detect brake state is released. | ||
1 = When PWM0 channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel3 at brake state, writing 1 to clear. | ||
[20] | BRKESTS4 | PWM0 Channel4 Edge-detect Brake Status (Read Only) |
0 = PWM0 channel4 edge-detect brake state is released. | ||
1 = When PWM0 channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel4 at brake state, writing 1 to clear. | ||
[21] | BRKESTS5 | PWM0 Channel5 Edge-detect Brake Status (Read Only) |
0 = PWM0 channel5 edge-detect brake state is released. | ||
1 = When PWM0 channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel5 at brake state, writing 1 to clear. | ||
[24] | BRKLSTS0 | PWM0 Channel0 Level-detect Brake Status (Read Only) |
0 = PWM0 channel0 level-detect brake state is released. | ||
1 = When PWM0 channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel0 at brake state. | ||
Note: This bit is read only and auto cleared by hardware | ||
When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
The PWM0 waveform will start output from next full PWM0 period. | ||
[25] | BRKLSTS1 | PWM0 Channel1 Level-detect Brake Status (Read Only) |
0 = PWM0 channel1 level-detect brake state is released. | ||
1 = When PWM0 channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel1 at brake state. | ||
Note: This bit is read only and auto cleared by hardware | ||
When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
The PWM0 waveform will start output from next full PWM0 period. | ||
[26] | BRKLSTS2 | PWM0 Channel2 Level-detect Brake Status (Read Only) |
0 = PWM0 channel2 level-detect brake state is released. | ||
1 = When PWM0 channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel2 at brake state. | ||
Note: This bit is read only and auto cleared by hardware | ||
When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
The PWM0 waveform will start output from next full PWM0 period. | ||
[27] | BRKLSTS3 | PWM0 Channel3 Level-detect Brake Status (Read Only) |
0 = PWM0 channel3 level-detect brake state is released. | ||
1 = When PWM0 channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel3 at brake state. | ||
Note: This bit is read only and auto cleared by hardware | ||
When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
The PWM0 waveform will start output from next full PWM0 period. | ||
[28] | BRKLSTS4 | PWM0 Channel4 Level-detect Brake Status (Read Only) |
0 = PWM0 channel4 level-detect brake state is released. | ||
1 = When PWM0 channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel4 at brake state. | ||
Note: This bit is read only and auto cleared by hardware | ||
When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
The PWM0 waveform will start output from next full PWM0 period. | ||
[29] | BRKLSTS5 | PWM0 Channel5 Level-detect Brake Status (Read Only) |
0 = PWM0 channel5 level-detect brake state is released. | ||
1 = When PWM0 channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel5 at brake state. | ||
Note: This bit is read only and auto cleared by hardware | ||
When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
The PWM0 waveform will start output from next full PWM0 period. |
PDMA_CH_T::INTSTSn |
[0x0024] PDMA channel n Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | TABTIF | PDMA Read/Write Target Abort Interrupt Status Flag |
0 = No bus ERROR response received. | ||
1 = Bus ERROR response received. | ||
Note1: This bit is cleared by writing 1 to it. | ||
Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that target abort is happened | ||
PDMA controller will stop transfer and respond this event to user then go to IDLE state | ||
When target abort occurred, user must reset PDMA controller, and then transfer those data again. | ||
[1] | TDIF | Transfer Done Interrupt Status Flag |
This bit indicates that PDMA has finished all transfer. | ||
0 = Not finished yet. | ||
1 = Done. | ||
Note: This bit is cleared by writing 1 to it. | ||
[6] | TOUTIF | Time-out Interrupt Status Flag |
This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC. | ||
0 = No time-out flag. | ||
1 = Time-out flag. | ||
Note: This bit is cleared by writing 1 to it. | ||
[8] | PCNTIF | Periodic Count Interrupt Status Flag |
This flag indicates PCNTITH (PDMA_CNTn[30:16], n=1~4) data has been transferred. | ||
Note: This bit is cleared by writing 1 to it. |
GPIO_T::INTTYPE |
[0x0018] Pn Interrupt Trigger Type Control
Bits | Field | Descriptions |
---|---|---|
[0] | TYPE0 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | TYPE1 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | TYPE2 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | TYPE3 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | TYPE4 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | TYPE5 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | TYPE6 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | TYPE7 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | TYPE8 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | TYPE9 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | TYPE10 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | TYPE11 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | TYPE12 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | TYPE13 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | TYPE14 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | TYPE15 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
0 = Edge trigger interrupt. | ||
1 = Level trigger interrupt. | ||
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
The de-bounce function is valid only for edge triggered interrupt | ||
If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
SYS_T::IPRST1 |
[0x0008] Peripheral Reset Control Resister1
Bits | Field | Descriptions |
---|---|---|
[0] | CHIPRST | Chip One-shot Reset (Write Protect) |
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. | ||
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. | ||
About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 | ||
0 = Chip normal operation. | ||
1 = Chip one-shot reset. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[1] | CPURST | Processor Core One-shot Reset (Write Protect) |
Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. | ||
0 = Processor core normal operation. | ||
1 = Processor core one-shot reset. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[2] | PDMARST | PDMA Controller Reset (Write Protect) |
Setting this bit to 1 will generate a reset signal to the PDMA | ||
User needs to set this bit to 0 to release from reset state. | ||
0 = PDMA controller normal operation. | ||
1 = PDMA controller reset. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
SYS_T::IPRST2 |
[0x000c] Peripheral Reset Control Resister2
Bits | Field | Descriptions |
---|---|---|
[1] | GPIORST | GPIO Controller Reset |
0 = GPIO module normal operation. | ||
1 = GPIO module reset. | ||
[2] | TMR0RST | Timer0 Controller Reset |
0 = Timer0 module normal operation. | ||
1 = Timer0 module reset. | ||
[3] | TMR1RST | Timer1 Controller Reset |
0 = Timer1 module normal operation. | ||
1 = Timer1 module reset. | ||
[4] | TMR2RST | Timer2 Controller Reset |
0 = Timer2 module normal operation. | ||
1 = Timer2 module reset. | ||
[5] | TMR3RST | Timer3 Controller Reset |
0 = Timer3 module normal operation. | ||
1 = Timer3 module reset. | ||
[8] | I2C0RST | I2C0 Controller Reset |
0 = I2C0 module normal operation. | ||
1 = I2C0 module reset. | ||
[9] | I2C1RST | I2C1 Controller Reset |
0 = I2C1 module normal operation. | ||
1 = I2C1 module reset. | ||
[12] | SPI0RST | SPI0 Controller Reset |
0 = SPI0 module normal operation. | ||
1 = SPI0 module reset. | ||
[13] | SPI1RST | SPI1 Controller Reset |
0 = SPI1 module normal operation. | ||
1 = SPI1 module reset. | ||
[14] | SPI2RST | SPI2 Controller Reset |
0 = SPI2 module normal operation. | ||
1 = SPI2 module reset. | ||
[15] | SPI3RST | SPI3 Controller Reset |
0 = SPI3 module normal operation. | ||
1 = SPI3 module reset. | ||
[16] | UART0RST | UART0 Controller Reset |
0 = UART0 module normal operation. | ||
1 = UART0 module reset. | ||
[17] | UART1RST | UART1 Controller Reset |
0 = UART1 module normal operation. | ||
1 = UART1 module reset. | ||
[20] | PWM0RST | PWM0 Controller Reset |
0 = PWM0 module normal operation. | ||
1 = PWM0 module reset. | ||
[22] | ACMP01RST | Comparator Controller Reset |
0 = Comparator module normal operation. | ||
1 = Comparator module reset. | ||
[28] | ADCRST | ADC Controller Reset |
0 = ADC module normal operation. | ||
1 = ADC module reset. | ||
[30] | SC0RST | SmartCard 0 Controller Reset |
0 = SmartCard module normal operation. | ||
1 = SmartCard module reset. | ||
[31] | SC1RST | SmartCard1 Controller Reset |
0 = SmartCard module normal operation. | ||
1 = SmartCard module reset. |
SYS_T::IRC0TCTL |
[0x0080] HIRC0 Trim Control Register
Bits | Field | Descriptions |
---|---|---|
[2:0] | FREQSEL | Trim Frequency Selection |
This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC0) auto trim. | ||
During auto trim operation, if clock error detected with CESTOPEN (SYS_IRC0TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 000 automatically. | ||
000 = Disable HIRC0 auto trim function. | ||
001 = Enable HIRC0 auto trim function and trim HIRC to 11.0592 MHz. | ||
010 = Enable HIRC0 auto trim function and trim HIRC to 12 MHz. | ||
011 = Enable HIRC0 auto trim function and trim HIRC to 12.288 MHz. | ||
100 = Enable HIRC0 auto trim function and trim HIRC to 16 MHz. | ||
Note: HIRC0 auto trim cannot work normally at power down mode | ||
These bits must be cleared before entering power down mode. | ||
[5:4] | LOOPSEL | Trim Calculation Loop Selection |
This field defines that trim value calculation is based on how many 32.768 kHz clock. | ||
00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. | ||
01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. | ||
10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. | ||
11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. | ||
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. | ||
[7:6] | RETRYCNT | Trim Value Update Limitation Count |
This field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked. | ||
Once the HIRC0 locked, the internal trim value update counter will be reset. | ||
If the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00. | ||
00 = Trim retry count limitation is 64 loops. | ||
01 = Trim retry count limitation is 128 loops. | ||
10 = Trim retry count limitation is 256 loops. | ||
11 = Trim retry count limitation is 512 loops. | ||
[8] | CESTOPEN | Clock Error Stop Enable Bit |
This bit is used to control if stop the HIRC0 trim operation when 32.768 kHz clock error is detected. | ||
If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation was stopped | ||
If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation is continuously. | ||
0 = The trim operation is keep going if clock is inaccuracy. | ||
1 = The trim operation is stopped if clock is inaccuracy. |
SYS_T::IRC0TIEN |
[0x0084] HIRC0 Trim Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit |
This bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC0 frequency still not locked on target frequency set by FREQSEL (SYS_IRC0TCTL[1:0]). | ||
If this bit is high and TFAILIF (SYS_IRC0TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. | ||
0 = Disable TFAILIF (SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU. | ||
1 = Enable TFAILIF (SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU. | ||
[2] | CLKEIEN | Clock Error Interrupt Enable Bit |
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. | ||
If this bit is set to1, and CLKERRIF (SYS_IRC0TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. | ||
0 = Disable CLKERRIF (SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU. | ||
1 = Enable CLKERRIF (SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU. |
SYS_T::IRC0TISTS |
[0x0088] HIRC0 Trim Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | FREQLOCK | HIRC0 Frequency Lock Status |
This bit indicates the HIRC0 frequency is locked. | ||
This is a status bit and doesn't trigger any interrupt. | ||
0 = The internal high-speed oscillator frequency doesn't lock at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]). | ||
1 = The internal high-speed oscillator frequency locked at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]). | ||
[1] | TFAILIF | Trim Failure Interrupt Status |
This bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked | ||
Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically. | ||
If this bit is set and TFAILIEN (SYS_IRC0TIEN[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached | ||
Write 1 to clear this to 0. | ||
0 = Trim value update limitation count does not reach. | ||
1 = Trim value update limitation count reached and HIRC frequency still not locked. | ||
[2] | CLKERRIF | Clock Error Interrupt Status |
When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy | ||
Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRC0TCTL[8]) is set to 1. | ||
If this bit is set and CLKEIEN (SYS_IRC0TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy | ||
Write 1 to clear this to 0. | ||
0 = Clock frequency is accuracy. | ||
1 = Clock frequency is inaccuracy. |
SYS_T::IRC1TCTL |
[0x0090] HIRC1 Trim Control Register
Bits | Field | Descriptions |
---|---|---|
[1:0] | FREQSEL | Trim Frequency Selection |
This field indicates the target frequency of 36 MHz internal high speed RC oscillator (HIRC1) auto trim. | ||
During auto trim operation, if clock error detected with CESTOPEN (SYS_IRC1TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. | ||
00 = Disable HIRC1 auto trim function. | ||
01 = Reserved | ||
10 = Enable HIRC1 auto trim function and trim HIRC to 36 MHz. | ||
11 = Reserved. | ||
Note: HIRC1 auto trim cannot work normally at power down mode | ||
These bits must be cleared before entering power down mode. | ||
[5:4] | LOOPSEL | Trim Calculation Loop Selection |
This field defines that trim value calculation is based on how many 32.768 kHz clock. | ||
00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. | ||
01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. | ||
10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. | ||
11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. | ||
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. | ||
[7:6] | RETRYCNT | Trim Value Update Limitation Count |
This field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked. | ||
Once the HIRC1 locked, the internal trim value update counter will be reset. | ||
If the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00. | ||
00 = Trim retry count limitation is 64 loops. | ||
01 = Trim retry count limitation is 128 loops. | ||
10 = Trim retry count limitation is 256 loops. | ||
11 = Trim retry count limitation is 512 loops. | ||
[8] | CESTOPEN | Clock Error Stop Enable Bit |
This bit is used to control if stop the HIRC1 trim operation when 32.768 kHz clock error is detected. | ||
If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation was stopped | ||
If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation is continuously. | ||
0 = The trim operation is keep going if clock is inaccuracy. | ||
1 = The trim operation is stopped if clock is inaccuracy. |
SYS_T::IRC1TIEN |
[0x0094] HIRC1 Trim Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit |
This bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL (SYS_IRC1TCTL[1:0]). | ||
If this bit is high and TFAILIF (SYS_IRC1TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. | ||
0 = Disable TFAILIF (SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU. | ||
1 = Enable TFAILIF (SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU. | ||
[2] | CLKEIEN | Clock Error Interrupt Enable Bit |
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. | ||
If this bit is set to1, and CLKERRIF (SYS_IRC1TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. | ||
0 = Disable CLKERRIF (SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU. | ||
1 = Enable CLKERRIF (SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU. |
SYS_T::IRC1TISTS |
[0x0098] HIRC1 Trim Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | FREQLOCK | HIRC1 Frequency Lock Status |
This bit indicates the HIRC1 frequency is locked. | ||
This is a status bit and doesn't trigger any interrupt. | ||
0 = The internal high-speed oscillator frequency doesn't lock at 36 MHz yet. | ||
1 = The internal high-speed oscillator frequency locked at 36 MHz. | ||
[1] | TFAILIF | Trim Failure Interrupt Status |
This bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked | ||
Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically. | ||
If this bit is set and TFAILIEN (SYS_IRC1TIEN[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached | ||
Write 1 to clear this to 0. | ||
0 = Trim value update limitation count does not reach. | ||
1 = Trim value update limitation count reached and HIRC1 frequency still not locked. | ||
[2] | CLKERRIF | Clock Error Interrupt Status |
When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 36 MHz internal high speed RC oscillator (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy | ||
Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRC1TCTL[8]) is set to 1. | ||
If this bit is set and CLKEIEN (SYS_IRC1TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy | ||
Write 1 to clear this to 0. | ||
0 = Clock frequency is accuracy. | ||
1 = Clock frequency is inaccuracy. |
UART_T::IRDA |
[0x0030] UART IrDA Control Register.
Bits | Field | Descriptions |
---|---|---|
[1] | TXEN | IrDA Receiver/Transmitter Selection Enable Bit |
0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) | ||
1 = IrDA Transmitter Enabled and Receiver Disabled. | ||
[5] | TXINV | IrDA Inverse Transmitting Output Signal |
0 = None inverse transmitting signal. (Default) | ||
1 = Inverse transmitting output signal. | ||
[6] | RXINV | IrDA Inverse Receive Input Signal |
0 = None inverse receiving input signal. | ||
1 = Inverse receiving input signal. (Default) |
INT_T::IRQ0_SRC |
INT_T::IRQ10_SRC |
INT_T::IRQ11_SRC |
INT_T::IRQ12_SRC |
INT_T::IRQ13_SRC |
INT_T::IRQ14_SRC |
INT_T::IRQ15_SRC |
INT_T::IRQ16_SRC |
INT_T::IRQ17_SRC |
INT_T::IRQ18_SRC |
INT_T::IRQ19_SRC |
INT_T::IRQ1_SRC |
INT_T::IRQ20_SRC |
INT_T::IRQ21_SRC |
INT_T::IRQ22_SRC |
INT_T::IRQ23_SRC |
INT_T::IRQ24_SRC |
INT_T::IRQ25_SRC |
INT_T::IRQ26_SRC |
INT_T::IRQ27_SRC |
INT_T::IRQ28_SRC |
INT_T::IRQ29_SRC |
INT_T::IRQ2_SRC |
INT_T::IRQ30_SRC |
INT_T::IRQ31_SRC |
INT_T::IRQ3_SRC |
INT_T::IRQ4_SRC |
INT_T::IRQ5_SRC |
INT_T::IRQ6_SRC |
INT_T::IRQ7_SRC |
INT_T::IRQ8_SRC |
INT_T::IRQ9_SRC |
FMC_T::ISPADDR |
[0x0004] ISP Address Register
Bits | Field | Descriptions |
---|---|---|
[31:0] | ISPADDR | ISP Address |
The Nano103 series is equipped with embedded flash | ||
ISPADDR [1:0] must be kept 00 for ISP 32-bit operation. | ||
For both CRC-32 Checksum Calculation and Flash All-One Verification commands, this field is the flash starting address for checksum calculation and 512 bytes address alignment is necessary. |
FMC_T::ISPCMD |
[0x000c] ISP CMD Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | CMD | ISP CMD |
ISP command table is shown below: | ||
0x00 = FLASH 32-bit Read. | ||
0x04 = Read Unique ID. | ||
0x08 = Read All-One Verification Result. | ||
0x0B = Read Company ID. | ||
0x0C = Read Device ID. | ||
0x0D = Read CRC-32 Checksum. | ||
0x21 = FLASH 32-bit Program. | ||
0x22 = FLASH Page Erase. | ||
0x26 = FLASH Mass Erase. | ||
0x28 = Run All-One Verification. | ||
0x2D = Run CRC-32 Checksum Calculation. | ||
0x2E = Vector Remap. | ||
The other commands are invalid. |
FMC_T::ISPCTL |
[0x0000] ISP Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | ISPEN | ISP Enable Bit (Write Protect) |
ISP function enable bit. Set this bit to enable ISP function. | ||
0 = ISP function Disabled. | ||
1 = ISP function Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[1] | BS | Boot Select (Write Protect) |
Set/clear this bit to select next booting from LDROM/APROM, respectively | ||
This bit also functions as chip booting status flag, which can be used to check where chip booted from. | ||
This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. | ||
0 = Booting from APROM. | ||
1 = Booting from LDROM. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[3] | APUEN | APROM Update Enable Bit (Write Protect) |
0 = APROM cannot be updated when the chip runs in APROM booting without IAP mode. | ||
1 = APROM can be updated when the chip runs in APROM booting without IAP mode | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[4] | CFGUEN | CONFIG Update Enable Bit (Write Protect) |
0 = CONFIG cannot be updated. | ||
1 = CONFIG can be updated. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[5] | LDUEN | LDROM Update Enable Bit (Write Protect) |
LDROM update enable bit. | ||
0 = LDROM cannot be updated. | ||
1 = LDROM can be updated. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
In LDROM booting without IAP mode, LDROM cannot be updated even if LDUEN=1. | ||
[6] | ISPFF | ISP Fail Flag (Write Protect) |
This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
This bit needs to be cleared by writing 1 to it. | ||
(1) APROM writes to itself if APUEN is set to 0. | ||
(2) LDROM writes to itself if LDUEN is set to 0. | ||
(3) CONFIG is erased/programmed if CFGUEN is set to 0. | ||
(6) Page Erase command at LOCK mode with ICE connection | ||
(7) Erase or Program command at brown-out detected | ||
(8) Destination address is illegal, such as over an available range. | ||
(9) Invalid ISP commands | ||
(10) KPROM is erased/programmed if KEYLOCK is set to 1 | ||
(11) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
FMC_T::ISPDAT |
[0x0008] ISP Data Register
Bits | Field | Descriptions |
---|---|---|
[31:0] | ISPDAT | ISP Data |
Write data to this register before ISP program operation. | ||
Read data from this register after ISP read operation. | ||
For Run CRC-32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment | ||
For ISP Read CRC-32 Checksum command, ISPDAT is the checksum result | ||
If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect. |
FMC_T::ISPSTS |
[0x0040] ISP Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | ISPBUSY | ISP Busy Flag (Read Only) |
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
This bit is the mirror of ISPGO(FMC_ISPTRG[0]). | ||
0 = ISP operation is finished. | ||
1 = ISP is progressed. | ||
[2:1] | CBS | Boot Selection of CONFIG (Read Only) |
This bit is initiated with the CBS (CONFIG0 [7:6]) after any reset is happened except CPU reset (CPURF(SYS_RSTSTS[7]) is 1) or system reset (SYSRF(SYS_RSTSTS[5]) is happened. | ||
00 = LDROM with IAP mode. | ||
01 = LDROM without IAP mode. | ||
10 = APROM with IAP mode. | ||
11 = APROM without IAP mode. | ||
[5] | PGFF | Flash Program with Fast Verification Flag(Read Only) |
This bit is set if data is mismatched at ISP programming verification | ||
This bit is clear by performing ISP flash erase or ISP read CID operation | ||
0 = Flash Program is success. | ||
1 = Flash Program is fail. Program data is different with data in the flash memory. | ||
[6] | ISPFF | ISP Fail Flag (Write Protect) |
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] | ||
This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
(1) APROM writes to itself if APUEN is set to 0. | ||
(2) LDROM writes to itself if LDUEN is set to 0. | ||
(3) CONFIG is erased/programmed if CFGUEN is set to 0. | ||
(4) Page Erase command at LOCK mode with ICE connection | ||
(5) Erase or Program command at brown-out detected | ||
(6) Destination address is illegal, such as over an available range. | ||
(7) Invalid ISP commands | ||
(8) KPROM is erased/programmed if KEYLOCK is set to 1 | ||
(9) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 | ||
Note: This bit is write-protected. Refer to the SYS_REGLCTL register. | ||
[7] | ALLONE | Flash All-one Verification Flag |
This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1. | ||
0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. | ||
1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. | ||
[29:9] | VECMAP | Vector Page Mapping Address (Read Only) |
All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF} | ||
VECMAP [20:19] = 00 system vector address is mapped to flash memory. | ||
VECMAP [20:19] = 10 system vector address is mapped to SRAM memory. | ||
VECMAP [18:12] should be 0. |
FMC_T::ISPTRG |
[0x0010] ISP Trigger Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | ISPGO | ISP Start Trigger (Write Protect) |
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
0 = ISP operation is finished. | ||
1 = ISP is progressed. | ||
Note:This bit is write protected. Refer to the SYS_REGLCTL register. |
SYS_T::IVREFCTL |
[0x006c] Internal Voltage Reference Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | BGPEN | Band-gap Enable Control (Write Protect) |
This is a protected register. Please refer to open lock sequence to program it. | ||
Band-gap is the reference voltage of internal reference voltage | ||
User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage. | ||
0 = Disabled. | ||
1 = Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[1] | REGEN | Regulator Enable Control (Write Protect) |
Enable internal 1.5, 1.8V or 2.5V reference voltage. | ||
This is a protected register. Please refer to open lock sequence to program it. | ||
0 = Disabled. | ||
1 = Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[3:2] | SEL25 | Regulator Output Voltage Selection (Write Protect) |
Select internal reference voltage level. | ||
00 = 1.5V. | ||
01 = 1.8V. | ||
10 = 2.5V. | ||
11 = 2.5V. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[4] | EXTMODE | Regulator External Mode (Write Protect) |
Users can output regulator output voltage in VREF pin if EXT_MODE is high. | ||
0 = No connection with external VREF pin. | ||
1 = Connect to external VREF pin | ||
Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[11:8] | VREFTRIM | Internal Voltage Reference Trim (Write Protect) |
Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
FMC_T::KECNT |
[0x0064] KEY-Unmatched Counting Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | KECNT | Error Key Entry Counter at Each Power-on (Read Only) |
KECNT is increased when entry keys is wrong in Security Key protection. | ||
KECNT is cleared to 0 if key comparison is matched or system power-on. | ||
[13:8] | KEMAX | Maximum Number for Error Key Entry at Each Power-on (Read Only). |
KEMAX is the maximum error key entry number at each power-on. | ||
When KEMAXROM of KPROM is erased or programmed, KEMAX will also be updated. | ||
KEMAX is used to limit KECNT(FMC_KECNT[5:0]) maximum counting. | ||
The FORBID (FMC_KEYSTS [3]) will be set to 1 when KECNT is more than KEMAX. |
FMC_T::KEY0 |
FMC_T::KEY1 |
FMC_T::KEY2 |
FMC_T::KEYSTS |
[0x0060] KEY Comparison Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | KEYBUSY | KEY Comparison Busy (Read Only) |
0 = KEY comparison is finished. | ||
1 = KEY comparison is busy. | ||
[1] | KEYLOCK | KEY LOCK Flag |
This bit is set to 1 if KEYMATCH (FMC_KEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection | ||
This bit also can be set to 1 while | ||
l CPU write 1 to KEYLOCK(FMC_KEYSTS[1]) or | ||
l KEYFLAG(FMC_KEYSTS[4]) is 1 at power-on or reset or | ||
l KEYENROM is programmed a non-0xFF value or | ||
l Time-out event or | ||
l FORBID(FMC_KEYSTS[3]) is 1 | ||
0 = KPROM and APROM (not include Data Flash) is not in write protection. | ||
1 = KPROM and APROM (not include Data Flash) is in write protection. | ||
CONFIG write protect is depended on CFGFLAG | ||
[2] | KEYMATCH | KEY Match Flag(Read Only) |
This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched | ||
This bit is also cleared to 0 while | ||
l CPU writing 1 to KEYLOCK(FMC_KEYSTS[1]) or | ||
l Time-out event or | ||
l KPROM is erased or | ||
l KEYENROM is programmed to a non-0xFF value. | ||
l Chip is in Power-down mode. | ||
0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. | ||
1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. | ||
[3] | FORBID | KEY Comparison Forbidden Flag(Read Only) |
This bit is set to 1 whenKECNT(FMC_KECNT[4:0])is more than KEMAX (FMC_KECNT[12:8]) orKPCNT (FMC_KPCNT [2:0])is more than KPMAX (FMC_KPCNT [10:8]). | ||
0 = KEY comparison is not forbidden. | ||
1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. | ||
[4] | KEYFLAG | KEY Protection Enable Flag(Read Only) |
This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset | ||
This bit is cleared to 0 by hardware while KPROM is erased | ||
This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. | ||
0 = Security Key protection Disabled. | ||
1 = Security KeyprotectionEnabled. | ||
[5] | CFGFLAG | CONFIG Write-protection Enable Flag(Read Only) |
This bit is set while the KEYENROM [0] is 0 at power-on or reset | ||
This bit is cleared to 0 by hardware while KPROM is erased | ||
This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. | ||
0 = CONFIG write-protection Disabled. | ||
1 = CONFIG write-protection Enabled. |
FMC_T::KEYTRG |
[0x005c] KEY Comparison Trigger Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | KEYGO | KEY Comparison Start Trigger (Write Protection) |
Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. | ||
This trigger operation is valid while FORBID (FMC_KEYSTS [3]) is 0. | ||
0 = KEY comparison operation is finished. | ||
1 = KEY comparison is progressed. | ||
Note:This bit is write-protected. Refer to the SYS_REGLCTL register. | ||
[1] | TCEN | Time-out Counting Enable Bit (Write Protection) |
0 = Time-out counting Disabled. | ||
1 = Time-out counting Enabled if key is matched after key comparison finish. | ||
10 minutes is at least for time-out, and average is about 20 minutes. | ||
Note:This bit is write-protected. Refer to the SYS_REGLCTL register. |
FMC_T::KPCNT |
[0x0068] KEY-Unmatched Power-on Counting Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | KPCNT | Power-on Counter for Error Key Entry(Read Only). |
KPCNT is the power-on counting for error key entry in Security Key protection. | ||
KPCNT is cleared to 0 if key comparison is matched. | ||
[11:8] | KPMAX | Power-on Maximum Number for Error Key Entry (Read Only). |
KPMAX is the power-on maximum number for error key entry. | ||
When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated. | ||
KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting. | ||
The FORBID(FMC_KEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX. |
SYS_T::LDOCTL |
[0x0070] LDO Control Register
Bits | Field | Descriptions |
---|---|---|
[1] | FASTWK | Fast Wakeup Control Bit (Write Protect) |
0 = Fast Wakeup from Power-Down mode Disabled. | ||
1 = Fast Wakeup from Power-Down mode Enabled | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[3:2] | LDOLVL | LDO Output Voltage Select (Write Protect) |
00 = 1.2V. | ||
01 = 1.6V. | ||
10 = 1.8V. | ||
11 = 1.8V. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[4] | LPRMEN | Low-Power Run Mode Enable Bit (Write Protect) |
0 = Low-Power run mode Enabled. | ||
1 = Low-Power run mode Disabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[5] | FMCLVEN | Flash memory Low voltage Mode Enable Bit (Write Protect) |
0 = Flash memory low voltage(1.2V) mode Enabled. | ||
1 = Flash memory low voltage(1.2V) mode Disabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
RTC_T::LEAPYEAR |
UART_T::LINE |
[0x0008] UART Transfer Line Control Register.
Bits | Field | Descriptions |
---|---|---|
[1:0] | WLS | Word Length Selection |
This field sets UART word length. | ||
00 = 5 bits. | ||
01 = 6 bits. | ||
10 = 7 bits. | ||
11 = 8 bits. | ||
[2] | NSB | Number of STOP Bit |
0 = One STOP bit is generated in the transmitted data. | ||
1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data | ||
When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data. | ||
[3] | PBE | Parity Bit Enable Bit |
0 = No parity bit generated Disabled. | ||
1 = Parity bit generated Enabled. | ||
Note: Parity bit is generated on each outgoing character and is checked on each incoming data. | ||
[4] | EPE | Even Parity Enable Bit |
0 = Odd number of logic 1's is transmitted and checked in each word. | ||
1 = Even number of logic 1's is transmitted and checked in each word. | ||
Note: This bit has effect only when PBE (UART_TLCTL[3]) is set. | ||
[5] | SPE | Stick Parity Enable Bit |
0 = Stick parity Disabled. | ||
1 = Stick parity Enabled. | ||
Note: If PBE (UART_TLCTL[3]) and EPE (UART_TLCTL[4]) are logic 1, the parity bit is transmitted and checked as logic 0 | ||
If PBE (UART_TLCTL[3]) is 1 and EPE (UART_TLCTL[4]) is 0 then the parity bit is transmitted and checked as 1. | ||
[6] | BCB | Break Control Bit |
0 = Break Control Disabled. | ||
1 = Break Control Enabled. | ||
Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) | ||
This bit acts only on TX line and has no effect on the transmitter logic. | ||
[9:8] | RFITL | RX FIFO Interrupt Trigger Level |
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_IER [0]) enabled, and an interrupt will be generated). | ||
0000 = RX FIFO Interrupt Trigger Level is 1 byte. | ||
0001 = RX FIFO Interrupt Trigger Level is 4 bytes. | ||
0010 = RX FIFO Interrupt Trigger Level is 8 bytes. | ||
0011 = RX FIFO Interrupt Trigger Level is 14 bytes. | ||
Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0. | ||
[13:12] | RTSTRGLV | nRTS Trigger Level for Auto-flow Control Use |
00 = nRTS Trigger Level is 1 byte. | ||
01 = nRTS Trigger Level is 4 bytes. | ||
10 = nRTS Trigger Level is 8 bytes. | ||
11 = nRTS Trigger Level is 14 bytes. | ||
Note: This field is used for auto nRTS flow control. |
RTC_T::LXTCTL |
RTC_T::LXTICTL |
[0x0108] X32KI Pin Control Register
Bits | Field | Descriptions |
---|---|---|
[1:0] | OPMODE | IO Operation Mode |
00 = X32KI (PF.7) is input only mode, without pull-up resistor. | ||
01 = X32KI (PF.7) is output push pull mode. | ||
10 = X32KI (PF.7) is open drain mode. | ||
11 = X32KI (PF.7) is input only mode with internal pull up. | ||
[2] | DOUT | IO Output Data |
0 = X32KI (PF.7) output low. | ||
1 = X32KI (PF.7) output high. | ||
[3] | CTLSEL | IO Pin State Backup Selection |
When low speed 32 kHz oscillator is disabled, X32KI (PF.7) pin can be used as GPIO function | ||
User can program CTLSEL bit to decide X32KI (PF.7) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register. | ||
0 = X32KI (PF.7) pin I/O function is controlled by GPIO module | ||
It becomes floating state when system power is turned off. | ||
1 = X32KI (PF.7) pin I/O function is controlled by VBAT power domain, X32KI (PF.7) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 | ||
I/O pin keeps the previous state after system power is turned off. | ||
Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1. |
RTC_T::LXTOCTL |
[0x0104] X32KO Pin Control Register
Bits | Field | Descriptions |
---|---|---|
[1:0] | OPMODE | GPF0 Operation Mode |
00 = X32KO (PF.6) is input only mode, without pull-up resistor. | ||
01 = X32KO (PF.6) is output push pull mode. | ||
10 = X32KO (PF.6) is open drain mode. | ||
11 = X32KO (PF.6) is input only mode with internal pull up. | ||
[2] | DOUT | IO Output Data |
0 = X32KO (PF.6) output low. | ||
1 = X32KO (PF.6) output high. | ||
[3] | CTLSEL | IO Pin State Backup Selection |
When low speed 32 kHz oscillator is disabled, X32KO (PF.6) pin can be used as GPIO function | ||
User can program CTLSEL bit to decide X32KO (PF.6) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register. | ||
0 = X32KO (PF.6) pin I/O function is controlled by GPIO module | ||
It becomes floating when system power is turned off. | ||
1 = X32KO (PF.6) pin I/O function is controlled by VBAT power domain, X32KO (PF.6) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 | ||
I/O pin keeps the previous state after system power is turned off. | ||
Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1. |
INT_T::MCU_IRQ |
[0x0084] MCU Interrupt Request Source Register
Bits | Field | Descriptions |
---|---|---|
[31:0] | MCU_IRQ | MCU IRQ Source Bits |
The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0 | ||
There are two modes to generate interrupt to Cortex-M0, the normal mode. | ||
The MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0. | ||
When the MCU_IRQ[n] is "0", setting MCU_IRQ[n] "1" will generate an interrupt to Cortex-M0 NVIC[n]. | ||
When the MCU_IRQ[n] is "1" (means an interrupt is asserted), setting the MCU_bit[n] will clear the interrupt | ||
Set MCU_IRQ[n] u201C0u201D: no any effect |
SYS_T::MIRCTCTL |
[0x00a0] MIRC Trim Control Register
Bits | Field | Descriptions |
---|---|---|
[1:0] | FREQSEL | Trim Frequency Selection |
This field indicates the target frequency of 4 MHz internal medium speed RC oscillator (MIRC) auto trim. | ||
During auto trim operation, if clock error detected with CESTOPEN (SYS_MIRCTCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. | ||
00 = Disable MIRC auto trim function. | ||
01 = Reserved. | ||
10 = Enable MIRC auto trim function and trim HIRC to 4 MHz. | ||
11 = Reserved. | ||
Note: MIRC auto trim cannot work normally at power down mode | ||
These bits must be cleared before entering power down mode. | ||
[5:4] | LOOPSEL | Trim Calculation Loop Selection |
This field defines that trim value calculation is based on how many 32.768 kHz clock. | ||
00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. | ||
01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. | ||
10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. | ||
11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. | ||
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. | ||
[7:6] | RETRYCNT | Trim Value Update Limitation Count |
This field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked. | ||
Once the MIRC locked, the internal trim value update counter will be reset. | ||
If the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00. | ||
00 = Trim retry count limitation is 64 loops. | ||
01 = Trim retry count limitation is 128 loops. | ||
10 = Trim retry count limitation is 256 loops. | ||
11 = Trim retry count limitation is 512 loops. | ||
[8] | CESTOPEN | Clock Error Stop Enable Bit |
This bit is used to control if stop the MIRC trim operation when 32.768 kHz clock error is detected. | ||
If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation was stopped | ||
If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation is continuously. | ||
0 = The trim operation is keep going if clock is inaccuracy. | ||
1 = The trim operation is stopped if clock is inaccuracy. |
SYS_T::MIRCTIEN |
[0x00a4] MIRC Trim Interrupt Enable Register
Bits | Field | Descriptions |
---|---|---|
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit |
This bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL (SYS_MIRCTCTL[1:0]). | ||
If this bit is high and TFAILIF (SYS_MIRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. | ||
0 = Disable TFAILIF (SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU. | ||
1 = Enable TFAILIF (SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU. | ||
[2] | CLKEIEN | Clock Error Interrupt Enable Bit |
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. | ||
If this bit is set to1, and CLKERRIF (SYS_MIRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. | ||
0 = Disable CLKERRIF (SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU. | ||
1 = Enable CLKERRIF (SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU. |
SYS_T::MIRCTISTS |
[0x00a8] MIRC Trim Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | FREQLOCK | MIRC Frequency Lock Status |
This bit indicates the MIRC frequency is locked. | ||
This is a status bit and doesn't trigger any interrupt. | ||
0 = The internal medium-speed oscillator frequency doesn't lock at 4 MHz yet. | ||
1 = The internal medium-speed oscillator frequency locked at 4 MHz. | ||
[1] | TFAILIF | Trim Failure Interrupt Status |
This bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked | ||
Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. | ||
If this bit is set and TFAILIEN (SYS_MIRCTIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached | ||
Write 1 to clear this to 0. | ||
0 = Trim value update limitation count does not reach. | ||
1 = Trim value update limitation count reached and MIRC frequency still not locked. | ||
[2] | CLKERRIF | Clock Error Interrupt Status |
When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 4 MHz internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy | ||
Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_MIRCTCTL[8]) is set to 1. | ||
If this bit is set and CLKEIEN (SYS_MIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy | ||
Write 1 to clear this to 0. | ||
0 = Clock frequency is accuracy. | ||
1 = Clock frequency is inaccuracy. |
SYS_T::MISCCTL |
[0x0014] Miscellaneous Control Resister
Bits | Field | Descriptions |
---|---|---|
[6] | POR33DIS | POR 33 Disable |
0 = POR33 is enable in normal operation. | ||
1 = POR33 is disable in normal operation. | ||
[7] | POR18DIS | POR 18 Disable |
0 = POR18 is enable in normal operation. | ||
1 = POR18 is disable in normal operation. |
RTC_T::MISCCTL |
GPIO_T::MODE |
[0x0000] Pn I/O Mode Control
Bits | Field | Descriptions |
---|---|---|
[1:0] | MODE0 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3:2] | MODE1 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5:4] | MODE2 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7:6] | MODE3 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9:8] | MODE4 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11:10] | MODE5 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13:12] | MODE6 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15:14] | MODE7 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[17:16] | MODE8 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[19:18] | MODE9 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[21:20] | MODE10 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[23:22] | MODE11 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[25:24] | MODE12 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[27:26] | MODE13 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[29:28] | MODE14 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[31:30] | MODE15 | Port A-f I/O Pin[N] Mode Control |
Determine each I/O mode of Px.n pins. | ||
00 = Px.n is in Input mode. | ||
01 = Px.n is in Push-pull Output mode. | ||
10 = Px.n is in Open-drain Output mode. | ||
11 = Reserved. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
UART_T::MODEM |
[0x001c] UART Modem Control Status Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RTSACTLV | nRTS Pin Active Level |
This bit defines the active level state of nRTS pin output. | ||
0 =n RTS pin output is high level active. | ||
1 = nRTS pin output is low level active. (Default) | ||
[1] | RTSSTS | nRTS Pin State (Read Only) |
This bit mirror from nRTS pin output of voltage logic status. | ||
0 = nRTS pin output is low level voltage logic state. | ||
1 = nRTS pin output is high level voltage logic state. | ||
[16] | CTSACTLV | nCTS Trigger Level |
This bit defines the active level state of nCTS pin input. | ||
0 = nCTS pin input is high level active. | ||
1 = nCTS pin input is low level active. (Default) | ||
[17] | CTSSTS | nCTS Pin Status (Read Only) |
This bit mirror from nCTS pin input of voltage logic status. | ||
0 = nCTS pin input is low level voltage logic state. | ||
1 = nCTS pin input is high level voltage logic state. | ||
Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. | ||
[18] | CTSDETF | Detect nCTS State Change Flag (Read Only) |
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_IER[3]). | ||
0 = nCTS input has not change state. | ||
1 = nCTS input has change state. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. |
PWM_T::MSK |
PWM_T::MSKEN |
[0x00b8] PWM0 Mask Enable Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | MSKENn | PWM0 Mask Enable Bits |
Each bit n controls the corresponding PWM0 channel n. | ||
The PWM0 output signal will be masked when this bit is enabled | ||
The corresponding PWM0 channel n will output MSKDATn (PWM0_MSK[5:0]) data. | ||
0 = PWM0 output signal is non-masked. | ||
1 = PWM0 output signal is masked and output MSKDATn data. |
INT_T::NMI_SEL |
PWM_T::PBUF0 |
PWM_T::PBUF2 |
PWM_T::PBUF4 |
SYS_T::PDID |
[0x0000] Part Device Identification Number Register
Bits | Field | Descriptions |
---|---|---|
[31:0] | PDID | Part Device Identification Number (Read Only) |
This register reflects device part number code | ||
Software can read this register to identify which device is used. |
ADC_T::PDMA |
SPI_T::PDMACTL |
[0x0038] SPI PDMA Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | TXPDMAEN | Transmit PDMA Enable Bit |
0 = Transmit PDMA function Disabled. | ||
1 = Transmit PDMA function Enabled. | ||
Refer to PDMA section for more detail information. | ||
SPI_CTL Note: | ||
1 | ||
Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode. | ||
2 | ||
If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period. | ||
Hardware will clear this bit to 0 automatically after PDMA transfer done. | ||
[1] | RXPDMAEN | Receiving PDMA Enable Bit |
0 = Receiver PDMA function Disabled. | ||
1 = Receiver PDMA function Enabled. | ||
Refer to PDMA section for more detail information. | ||
Note: | ||
Hardware will clear this bit to 0 automatically after PDMA transfer done. | ||
In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock | ||
[2] | PDMARST | PDMA Reset |
It is used to reset the SPI PDMA function into default state. | ||
0 = After reset PDMA function or in normal operation. | ||
1 = Reset PDMA function. | ||
Note: it is auto cleared to 0 after the reset function has done. |
PWM_T::PERIOD |
[0x0030] PWM0 Period Register 0,2,4
Bits | Field | Descriptions |
---|---|---|
[15:0] | PERIOD | PWM0 Period Register |
Up-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, and restarts from 0. | ||
Down-Count mode: In this mode, PWM0 counter counts from PERIOD to 0, and restarts from PERIOD. | ||
PWM0 period time = (PERIOD+1) * PWM0_CLK period. | ||
Up-Down-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, then decrements to 0 and repeats again. | ||
PWM0 period time = 2 * PERIOD * PWM0_CLK period. |
GPIO_T::PIN |
[0x0010] Pn Pin Value
Bits | Field | Descriptions |
---|---|---|
[0] | PIN0 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | PIN1 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | PIN2 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | PIN3 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | PIN4 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | PIN5 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | PIN6 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | PIN7 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | PIN8 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | PIN9 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | PIN10 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | PIN11 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | PIN12 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | PIN13 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | PIN14 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | PIN15 | Port A-f Pin[N] Pin Value |
Each bit of the register reflects the actual status of the respective Px.n pin | ||
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
SC_T::PINCTL |
[0x0024] SC Pin Control State Register.
Bits | Field | Descriptions |
---|---|---|
[0] | PWREN | SC_PWREN Pin Signal |
Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level. | ||
Write this field to drive SC_PWR pin | ||
Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level. | ||
Read this field to get SC_PWR pin status. | ||
0 = SC_PWR pin status is low. | ||
1 = SC_PWR pin status is high. | ||
Note: When operating at hardware activation, warm reset or deactivation mode, this bit will be changed automatically | ||
Thus,do not fill in this field when operating in these modes. | ||
[1] | SCRST | SC_RST Pin Signal |
This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit. | ||
Write this field to drive SC_RST pin. | ||
0 = Drive SC_RST pin to low. | ||
1 = Drive SC_RST pin to high. | ||
Read this field to get SC_RST pin status. | ||
0 = SC_RST pin status is low. | ||
1 = SC_RST pin status is high. | ||
Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically | ||
Thus,do not fill in this field when operating in these modes. | ||
[2] | CREMOVE | Card Detect Removal Status of SC_CD Pin (Read Only) |
This bit is set whenever card has been removal. | ||
0 = No effect. | ||
1 = Card removed. | ||
Note1: This bit is read only, but it can be cleared by writing u201C1u201D to it. | ||
Note2: Card detect engine will start after SCEN (SC_CTL[0])set. | ||
[3] | CINSERT | Card Detect Insert Status of SC_CD Pin (Read Only) |
This bit is set whenever card has been inserted. | ||
0 = No effect. | ||
1 = Card insert. | ||
Note1: This bit is read only, but it can be cleared by writing u201C1u201D to it. | ||
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set. | ||
[4] | CDPINSTS | Card Detect Status of SC_CD Pin Status (Read Only) |
This bit is the pin status flag of SC_CD | ||
0 = The SC_CD pin state at low. | ||
1 = The SC_CD pin state at high. | ||
[6] | CLKKEEP | SC Clock Enable Bit |
0 = SC clock generation Disabled. | ||
1 = SC clock always keeps free running. | ||
Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically | ||
Thus,do not fill in this field when operating in these modes. | ||
[7] | ADACEN | Auto Deactivation When Card Removal |
0 = Auto deactivation Disabled when hardware detected the card removal. | ||
1 = Auto deactivation Enabled when hardware detected the card removal. | ||
Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set) | ||
If this process completes, hardware will generate an interrupt INITIF to CPU. | ||
[9] | SCDOUT | SC Data Output Pin |
This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit. | ||
0 = Drive SCDATOUT pin to low. | ||
1 = Drive SCDATOUT pin to high. | ||
Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically | ||
Thus,do not fill in this field when SC is in these modes. | ||
[10] | CDLV | Card Detect Level |
0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected. | ||
1 = When hardware detects the card detect pin from low to high, it indicates a card is detected. | ||
Note: Software must select card detect level before activate Smart Card. | ||
[11] | PWRINV | SC_POW Pin Inverse |
This bit is used for inverse the SC_POW pin. | ||
There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]) | ||
PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection. | ||
00 = SC_POW_ Pin is 0. | ||
01 = SC_POW _Pin is 1. | ||
10 = SC_POW _Pin is 1. | ||
11 = SC_POW_ Pin is 0. | ||
Note:Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]). | ||
[16] | DATSTS | SC Data Input Pin Status (Read Only) |
This bit is the pin status of SC_DAT | ||
0 = The SC_DAT pin is low. | ||
1 = The SC_DAT pin is high. | ||
[30] | SYNC | SYNC Flag Indicator(Read Only) |
Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register. | ||
0 = Synchronizing is completion, user can write new data to SC_PINCTL register. | ||
1 = Last value is synchronizing. |
CLK_T::PLLCTL |
[0x0024] PLL Control Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | PLLMLP | PLL Multiple |
000000: Reserved | ||
000001: X1 | ||
000010: X2 | ||
000011: X3 | ||
000100: X4 | ||
... | ||
010000:X16 | ||
... | ||
100000: X32 | ||
100100: X36 | ||
0thers: Reserved | ||
PLL output frequency: PLL input frequency * PLLMLP. | ||
PLL output frequency range: 16MHz ~ 36MHz | ||
[13:8] | INDIV | PLL Input Source Divider |
The PLL input clock frequency = (PLL Clock Source frequency) / (INDIV + 1). | ||
PLL input clock frequency range: 0.8MHz ~ 2MHz | ||
[15:14] | STBTSEL | PLL Stable Time Selection |
00 = 100 cycle time of input clock source. | ||
01 = 120 cycle time of input clock source. | ||
10 = 180 cycle time of input clock source. | ||
11 = 240 cycle time of input clock source. | ||
[16] | PD | Power-down Mode |
If set the PDEN bit 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too | ||
0 = PLL is in normal mode. | ||
1 = PLL is in power-down mode (default). | ||
[18:17] | PLLSRC | PLL Source Clock Select |
00 = PLL source clock from HXT. | ||
01 = PLL source clock from HIRC0 or HIRC1. | ||
10 = PLL source clock from MIRC | ||
11 = reserved. |
PWM_T::POEN |
PWM_T::POLCTL |
[0x00d4] PWM0 Pin Polar Inverse Register
Bits | Field | Descriptions |
---|---|---|
[5:0] | PINVn | PWM0 PIN Polar Inverse Control |
The register controls polarity state of PWM0 output | ||
Each bit n controls the corresponding PWM0 channel n. | ||
0 = PWM0 output polar inverse Disabled. | ||
1 = PWM0 output polar inverse Enabled. |
SYS_T::PORCTL |
[0x0060] Power-On-Reset Controller Register
Bits | Field | Descriptions |
---|---|---|
[15:0] | POROFF | Power-on Reset Enable Bit (Write Protect) |
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again | ||
User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. | ||
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: | ||
nRESET, Watchdog, BOD reset, ICE reset command and the software-chip reset function. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
TIMER_T::PRECNT |
[0x0004] Timer Pre-Scale Counter Register
Bits | Field | Descriptions |
---|---|---|
[7:0] | PSC | Prescale Counter |
Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter | ||
If this field is 0 (PSC = 0), then there is no scaling. | ||
Note: If the PSC value is changed, CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded. |
GPIO_T::PUEN |
[0x0024] Pn Pull-Up Enable Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | PUEN0 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[1] | PUEN1 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[2] | PUEN2 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[3] | PUEN3 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[4] | PUEN4 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[5] | PUEN5 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[6] | PUEN6 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[7] | PUEN7 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[8] | PUEN8 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[9] | PUEN9 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[10] | PUEN10 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[11] | PUEN11 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[12] | PUEN12 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[13] | PUEN13 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[14] | PUEN14 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
[15] | PUEN15 | Port A-f Pin[N] Pull-up Enable Bit |
Read : | ||
0 = Px.n internal pull-up resistor Disabled. | ||
1 = Px.n internal pull-up resistor Enabled. | ||
Note1: | ||
Max. n=15 for port A/B/C/D/E. | ||
Max. n=7 for port F. | ||
Note2: | ||
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
ADC_T::PWD |
[0x0064] A/D Power Management Register
Bits | Field | Descriptions |
---|---|---|
[0] | PWUPRDY | ADC Power-up Sequence Completed and Ready for Conversion |
0 = ADC is not ready for conversion, it may be in power saving state or in the progress of power up. | ||
1 = ADC is ready for conversion. | ||
[1] | PWDCALEN | Power Up Calibration Function Enable Bit |
0 = Power up without calibration. | ||
1 = Power up with calibration. | ||
Note: This bit works together with CALSEL (ADC_CALCTL[3]), see the following | ||
{PWDCALEN,CALFBSEL} Description: | ||
PWDCALEN is 0 and CALFBSEL is 0: No need to calibrate. | ||
PWDCALEN is 0 and CALFBSEL is 1: No need to calibrate. | ||
PWDCALEN is 1 and CALFBSEL is 0: Load calibration word when power up. | ||
PWDCALEN is 1 and CALFBSEL is 1: Calibrate when power up. | ||
[3:2] | PWDMOD | ADC Power Saving Mode |
Set this bit fields to select ADC power saving mode. | ||
00 = Reserved. | ||
01 = ADC Power-down mode. | ||
10 = ADC Standby mode. | ||
11 = Reserved. | ||
Note1: Different power saving mode has different power down/up sequence | ||
To avoid ADC powering up with wrong sequence, user must keep PWMOD (ADC_PWD[3:2]) consistent each time in power down and power up. | ||
Note2: While the ADC is powered up from power saving mode (set to 00b/01b/11b) without calibration, the PWDCALEN(ADC_PWD[1]) is set to 0, and the calibration value will be reset. |
CLK_T::PWRCTL |
[0x0000] System Power-down Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | HXTEN | HXT Enable Bit (Write Protect) |
0 = 4~32 MHz external high speed crystal (HXT) Disabled. | ||
1 = 4~32 MHz external high speed crystal (HXT) Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[1] | LXTEN | LXT Enable Bit (Write Protect) |
0 = 32.768 kHz external low speed crystal (LXT) Disabled. | ||
1 = 32.768 kHz external low speed crystal (LXT) Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[2] | HIRC0EN | HIRC0 Enable Bit (Write Protect) |
0 = 12~16 MHz internal high speed RC oscillator (HIRC0) Disabled. | ||
1 = 12~16 MHz internal high speed RC oscillator (HIRC0) Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[3] | LIRCEN | LIRC Enable Bit (Write Protect) |
0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. | ||
1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[4] | PDWKDLY | Enable the Wake-up Delay Counter (Write Protect) |
When the chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait system clock stable when chip works at 4~32 MHz external high speed crystal oscillator (HXT). | ||
0 = Clock cycles delay Disabled. | ||
1 = Clock cycles delay Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[5] | PDWKIEN | Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect) |
0 = Power-down mode wake-up interrupt Disabled. | ||
1 = Power-down mode wake-up interrupt Enabled. | ||
Note1: The interrupt (EINT0~1, GPIO,, UART0~1, WDT, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or SPI0 ~3 )will occur when PDWKIEN are high. | ||
Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[6] | PDEN | System Power-Down Enable (Write Protect) |
When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit. | ||
(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set | ||
(default) | ||
(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. | ||
When chip wakes up from Power-down mode, this bit is auto cleared | ||
Users need to set this bit again for next Power-down. | ||
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. | ||
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection | ||
The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. | ||
0 = Chip operating normally or chip in idle mode because of WFI command. | ||
1 = Chip enters Power-down mode instant or wait CPU sleep command WFI. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[8] | HXTSLTYP | HXT Mode Selection (Write Protect) |
0 = High frequency crystal loop back path Disabled. It is used for external oscillator. | ||
1 = High frequency crystal loop back path Enabled. It is used for external crystal. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[12:10] | HXTGAIN | HXT Gain Control Bit (Write Protect) |
Gain control is used to enlarge the gain of crystal to make sure crystal wok normally | ||
If gain control is enabled, crystal will consume more power than gain control off. | ||
000= HXT frequency is lower than from 4 MHz. | ||
001 = HXT frequency is from 4 MHz to 8 MHz. | ||
010 = HXT frequency is from 8 MHz to 12 MHz. | ||
011= HXT frequency is from 12 MHz to 16 MHz. | ||
100 = HXT frequency is from 16 MHz to 24 MHz. | ||
101 = HXT frequency is from 24 MHz to 32 MHz. | ||
110 = HXT frequency is from 32 MHz to 36 MHz. | ||
111 = HXT frequency is higher than 36 MHz. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[13] | HIRC0FSEL | HIRC0 Output Frequency Select Bit |
0 = HIRC0 will output 12MHz clock. | ||
1 = HIRC0 will output 16MHz Clock. | ||
[14] | HIRC0FSTOP | HIRC0 Stop Output When Frequency Changes (Write Protect) |
0 = HIRC0 will continue to output when HIRC frequency changes. | ||
1 = HIRC0 will suppress to output during first 16 clocks when HIRC frequency change. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[24] | HIRC1EN | HIRC1 Enable Bit (Write Protect) |
0 = 36 MHz internal high speed RC oscillator (HIRC1) Disabled. | ||
1 = 36 MHz internal high speed RC oscillator (HIRC1) Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
[25] | MIRCEN | MIRC Enable Bit (Write Protect) |
0 = 4 MHz internal medium speed RC oscillator (MIRC) Disabled. | ||
1 = 4 MHz internal medium speed RC oscillator (MIRC) Enabled. | ||
Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
PWM_T::RCAPDAT0 |
PWM_T::RCAPDAT1 |
PWM_T::RCAPDAT2 |
PWM_T::RCAPDAT3 |
PWM_T::RCAPDAT4 |
PWM_T::RCAPDAT5 |
SYS_T::RCCFCTL |
[0x0028] RC Clock Filter Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | HIRC0FEN | HIRC0 Clock Filter Enable Bit |
This bit is used to enable/disable HIRC0 clock filter function. | ||
0 = HIRC0 clock filter function Disabled. | ||
1 = HIRC0 clock filter function Enabled (default). | ||
[1] | HIRC1FEN | HIRC1 Clock Filter Enable Bit |
This bit is used to enable/disable HIRC1 clock filter function. | ||
0 = HIRC1 clock filter function Disabled. | ||
1 = HIRC1 clock filter function Enabled (default). | ||
[2] | MRCFEN | MRC Clock Filter Enable Bit |
This bit is used to enable/disable MRC clock filter function. | ||
0 = 4MHz MRC clock filter function Disabled. | ||
1 = 4MHz MRC clock filter function Enabled (default). |
SYS_T::REGLCTL |
[0x0100] Register Lock Control Register
Bits | Field | Descriptions |
---|---|---|
[7:0] | REGLCTL | Register Lock Control Code (Write Only) |
Some registers have write-protection function | ||
Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field | ||
After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. | ||
Register Lock Control Disable Index (Read Only) | ||
0 = Write-protection Enabled for writing protected registers | ||
Any write to the protected register is ignored. | ||
1 = Write-protection Disabled for writing protected registers. |
DMA_GCR_T::REQSEL0 |
[0x0004] PDMA Request Source Select Register 0
Bits | Field | Descriptions |
---|---|---|
[12:8] | REQSRC1 | Channel 1 Request Source Selection |
This filed defines which peripheral is connected to PDMA channel 1 | ||
User can configure the peripheral by setting CH1_SEL. | ||
00000 = Connect to SPI0_TX. | ||
00001 = Connect to SPI1_TX. | ||
00010 = Connect to UART0_TX. | ||
00011 = Connect to UART1_TX. | ||
00100 = Reserved. | ||
00101 = Connect to SPI3_TX. | ||
00110 = Reserved. | ||
00111 = Reserved. | ||
01000 = Connect to SPI2_TX. | ||
01001 = Connect to TMR0. | ||
01010 = Connect to TMR1. | ||
01011 = Connect to TMR2. | ||
01100 = Connect to TMR3. | ||
10000 = Connect to SPI0_RX. | ||
10001 = Connect to SPI1_RX. | ||
10010 = Connect to UART0_RX. | ||
10011 = Connect to UART1_RX. | ||
10100 = Reserved. | ||
10101 = Connect to SPI3_RX. | ||
10110 = Connect to ADC. | ||
10111 = Reserved. | ||
11000 = Connect to SPI2_RX. | ||
11001 = Reserved. | ||
11010 = Reserved. | ||
11011 = Reserved. | ||
11100 = Reserved. | ||
Others = Disable to connected any peripheral. | ||
[20:16] | REQSRC2 | Channel 2 Request Source Selection |
This filed defines which peripheral is connected to PDMA channel 2 | ||
User can configure the peripheral setting by REQSRC2. | ||
Note: The channel configuration is the same as REQSRC1 field | ||
Please refer to the explanation of REQSRC1. | ||
[28:24] | REQSRC3 | Channel 3 Request Source Selection |
This filed defines which peripheral is connected to PDMA channel 3 | ||
User can configure the peripheral setting by REQSRC3. | ||
Note: The channel configuration is the same as REQSRC1 field | ||
Please refer to the explanation of REQSRC1. |
DMA_GCR_T::REQSEL1 |
[0x0008] PDMA Request Source Select Register 1
Bits | Field | Descriptions |
---|---|---|
[4:0] | REQSRC4 | Channel 4 Request Source Selection |
This filed defines which peripheral is connected to PDMA channel 4 | ||
User can configure the peripheral setting by REQSRC4. | ||
Note: The channel configuration is the same as REQSRC1 field | ||
Please refer to the explanation of REQSRC1. |
WWDT_T::RLDCNT |
[0x0000] Window Watchdog Timer Reload Counter Register
Bits | Field | Descriptions |
---|---|---|
[31:0] | WWDT_RLD | Window Watchdog Timer Reload Counter Register |
Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. | ||
Note: This register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal. |
SYS_T::RPDBCLK |
[0x0120] Reset Pin Debounce Clock Selection Register
Bits | Field | Descriptions |
---|---|---|
[6] | RSTPDBCLK | Reset Pin Debounce Clock Selection Bit |
Before switch clock, both clock sources must be enabled. | ||
0 = MIRC is selected as reset pin debounce clock. | ||
1 = HIRC0 is selected as reset pin debounce clock.(default) |
SYS_T::RSTSTS |
[0x0004] System Reset Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | PORF | POR Reset Flag |
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. | ||
0 = No reset from POR or CHIPRST. | ||
1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. | ||
Note: Write 1 to clear this bit to 0. | ||
[1] | PINRF | NRESET Pin Reset Flag |
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. | ||
0 = No reset from nRESET pin. | ||
1 = Pin nRESET had issued the reset signal to reset the system. | ||
Note: Write 1 to clear this bit to 0. | ||
[2] | WDTRF | WDT Reset Flag |
The WDT reset flag is set by the Reset Signal from the Watchdog Timer to indicate the previous reset source. | ||
0 = No reset from watchdog timer or window watchdog timer. | ||
1 = The watchdog timer had issued the reset signal to reset the system. | ||
Note: Write 1 to clear this bit to 0. | ||
[3] | LVRF | LVR Reset Flag |
The LVR reset flag is set by the Reset Signal from the Low-Voltage Reset controller to indicate the previous reset source. | ||
0 = No reset from LVR. | ||
1 = The LVR had issued the reset signal to reset the system. | ||
Note: Write 1 to clear this bit to 0. | ||
[4] | BODRF | BOD Reset Flag |
The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source. | ||
0 = No reset from BOD. | ||
1 = The BOD had issued the reset signal to reset the system. | ||
Note: Write 1 to clear this bit to 0. | ||
[5] | SYSRF | System Reset Flag |
The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source. | ||
0 = No reset from Cortex-M0. | ||
1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core. | ||
Note: Write 1 to clear this bit to 0. | ||
[7] | CPURF | CPU Reset Flag |
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC). | ||
0 = No reset from CPU. | ||
1 = The Cortex-M0 Core and FMC are reset by software setting CPURST to 1. | ||
Note: Write 1 to clear this bit to 0. | ||
[8] | LOCKRF | Lockup Reset Flag |
0 = No reset from Cortex-M0. | ||
1 = The Cortex-M0 had issued the reset signal to reset the system by Cortex-M0 lockup event. |
RTC_T::RWEN |
[0x0004] RTC Access Enable Register
Bits | Field | Descriptions |
---|---|---|
[15:0] | RWEN | RTC Register Access Enable Password (Write Only) |
Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock. | ||
Writing other value will clear RWENF. | ||
[16] | RWENF | RTC Register Access Enable Flag (Read Only) |
0 = RTC register read/write Disabled. | ||
1 = RTC register read/write Enabled. | ||
This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock . | ||
Note: RWENF will be mask to 0 during RTCBUSY = 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. | ||
[24] | RTCBUSY | RTC Write Busy Flag |
0: RTC write access enable | ||
1: RTC write access disable , RTC under Busy Status. | ||
Note: BUSY By Exceed RTC IP Processing Write Counter Capacity ( 6 counts Per 1120 PCLK cycles) . |
SPI_T::RX0 |
[0x0010] SPI Receive Data FIFO Register 0
Bits | Field | Descriptions |
---|---|---|
[31:0] | RX | Receive Data Register (Read Only) |
The received data can be read on it | ||
If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not. | ||
Note: The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22]) is set 1 | ||
The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode | ||
SPI_RX0 shall be read first in TWOBIT mode. | ||
In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. |
SPI_T::RX1 |
[0x0014] SPI Receive Data FIFO Register 1
Bits | Field | Descriptions |
---|---|---|
[31:0] | RX | Receive Data Register (Read Only) |
The received data can be read on it | ||
If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not. | ||
Note: The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22]) is set 1 | ||
The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode | ||
SPI_RX0 shall be read first in TWOBIT mode. | ||
In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. |
SC_T::RXTOUT |
[0x0010] SC Receive buffer Time-out Register.
Bits | Field | Descriptions |
---|---|---|
[8:0] | RFTM | SC Receiver FIFO Time-out |
The time-out counter resets and starts counting whenever the RX buffer received a new data word | ||
Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ). | ||
Note1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5. | ||
Note2: Filling in all 0 to this field indicates to disable this function. |
PDMA_CH_T::SAn |
DMA_CRC_T::SEED |
PWM_T::SELFTEST |
RTC_T::SPR |
[0x0040] ~ [0x0050] RTC Spare Register 0 ~ 4
Bits | Field | Descriptions |
---|---|---|
[31:0] | SPARE | Spare Register |
This field is used to store back-up information defined by user. | ||
This field will be cleared by hardware automatically once a snooper pin event is detected. | ||
Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled. |
RTC_T::SPRCTL |
[0x003c] RTC Spare Functional Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | SNPDEN | Snoop Detection Enable Bit |
0 = TAMPER pin detection is Disabled. | ||
1 = TAMPER pin detection is Enabled. | ||
[1] | SNPTYPE0 | Snoop Detection Level |
This bit controls TAMPER detect event is rising edge or falling edge. | ||
0 = Rising edge detection. | ||
1 = Falling edge detection. | ||
[2] | SPRRWEN | Spare Register Enable Bit |
0 = Spare register is Disabled. | ||
1 = Spare register is Enabled. | ||
Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed | ||
Did not change the content of the spare register, but read data all 0. | ||
[5] | SPRCSTS | SPR Clear Flag |
This bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify snoop event is detected. | ||
0 = Spare register content is not cleared. | ||
1 = Spare register content is cleared. | ||
Writes 1 to clear this bit. |
SPI_T::SSCTL |
[0x000c] SPI Slave Select Control Register
Bits | Field | Descriptions |
---|---|---|
[1:0] | SS | Slave Selection Control (Master Only) |
If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state (the same as SPI_CTL[1] for SPI_SS1). | ||
If AUTOSS = 0,. | ||
00 = Both SPI_SS1 and SPI_SS0 are inactive. | ||
01 = SPI_SS1 is inactive, SPI_SS0 is active. | ||
10 = SPI_SS1 is active, SPI_SS0 is inactive. | ||
11 = Both SPI_SS1 and SPI_SS0 are active. | ||
If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPI_SS0/SPI_SS1 line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time | ||
(The active level of SPI_SS1/SPI_SS0 is specified in SSACTPOL). | ||
If AUTOSS =1,. | ||
00 = Both SPI_SS1 and SPI_SS0 are inactive. | ||
01 = SPI_SS1 is inactive, SPI_SS0 is active on the duration of transaction. | ||
10 = SPI_SS1 is active on the duration of transaction, SPI_SS0 is inactive. | ||
11 = Both SPI_SS1 and SPI_SS0 are active on the duration of transaction. | ||
Note: | ||
1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. | ||
2. SPI_SS0 is also defined as device/slave select input in Slave mode | ||
And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software | ||
[2] | SSACTPOL | Slave Selection Active Polarity |
It defines the active polarity of slave selection signal (SPI_SS[1:0]). | ||
0 = The SPI_SS slave select signal is active Low. | ||
1 = The SPI_SS slave select signal is active High. | ||
[3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) |
0 = If this bit is set as 0, slave select signals are asserted and de-asserted by setting and clearing related bits in SS[1:0] (SPI_CTL[1:0]). | ||
1 = If this bit is set as 1, SPI_SS0 and SPI_SS1 signals are generated automatically | ||
It means that device/slave select signal, which is set in SS[1:0] (SPI_CTL[1:0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done. | ||
[4] | SSLTRIG | Slave Select Level Trigger Control |
0 = The input slave select signal is edge-trigger. | ||
1 = The slave select signal will be level-trigger | ||
It depends on SSACTPOL to decide the signal is active low or active high. | ||
[5] | SLV3WIRE | Slave 3-wire Mode Enable Bit |
This bit is used to ignore the slave select signal in Slave mode | ||
The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. | ||
0 = The controller is 4-wire bi-direction interface. | ||
1 = The controller is 3-wire bi-direction interface in Slave mode | ||
When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input. | ||
Note 1: Refer to No Slave Select Mode. | ||
Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically. | ||
[6] | SLVTOIEN | Slave Time-out Interrupt Enable Bit |
This bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur | ||
0 = Slave time-out function and interrupt both Disabled. | ||
1 = Slave time-out function and interrupt both Enabled. | ||
[8] | SLVABORT | Abort in Slave Mode with No Slave Selected |
0 = No force the slave abort. | ||
1 = Force the current transfer done in no slave select mode. | ||
Refer to No Slave Select Mode. | ||
Note: It is auto cleared to 0 by hardware when the abort event is active. | ||
[9] | SSTAIEN | Slave Start Interrupt Enable Bit |
0 = Transfer start interrupt Disabled in no slave select mode. | ||
1 = Transaction start interrupt Enabled in no slave select mode | ||
It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear). | ||
Refer to No Slave Select Mode. | ||
[16] | SSINAIEN | Slave Select Inactive Interrupt Enable Bit |
It is used to enable the interrupt when the transfer has done in slave mode. | ||
0 = No any interrupt, even there is slave select inactive event. | ||
1 = There is interrupt event when the slave select becomes inactive from active condition | ||
It is used to inform the user to know that the transaction has finished and the slave select into the inactive state. | ||
[29:20] | SLVTOCNT | Slave Mode Time-out Period |
In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active | ||
The clock source of the time-out counter is Slave peripheral clock | ||
If the value is 0, it indicates the slave mode time-out function is disabled. |
CLK_T::STATUS |
[0x000c] Clock status monitor Register
Bits | Field | Descriptions |
---|---|---|
[0] | HXTSTB | HXT Clock Source Stable Flag (Read Only) |
0 = 4~36 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. | ||
1 = 4~36 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. | ||
[1] | LXTSTB | LXT Clock Source Stable Flag (Read Only) |
0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. | ||
1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. | ||
[2] | PLLSTB | Internal PLL Clock Source Stable Flag (Read Only) |
0 = Internal PLL clock is not stable or disabled. | ||
1 = Internal PLL clock is stable and enabled. | ||
[3] | LIRCSTB | LIRC Clock Source Stable Flag (Read Only) |
0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. | ||
1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. | ||
[4] | HIRC0STB | HIRC0 Clock Source Stable Flag (Read Only) |
0 = 12~16 MHz internal high speed RC oscillator (HIRC0) clock is not stable or disabled. | ||
1 = 12~16 MHz internal high speed RC oscillator (HIRC0) clock is stable and enabled. | ||
[5] | HIRC1STB | HIRC Clock Source Stable Flag (Read Only) |
0 = 36 MHz internal high speed RC oscillator (HIRC1) clock is not stable or disabled. | ||
1 = 36 MHz internal high speed RC oscillator (HIRC1) clock is stable and enabled. | ||
[6] | MIRCSTB | MIRC Clock Source Stable Flag (Read Only) |
0 = 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled. | ||
1 = 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled. | ||
[7] | CLKSFAIL | Clock Switching Fail Flag (Read Only) |
This bit is updated when software switches system clock source | ||
If switch target clock is stable, this bit will be set to 0 | ||
If switch target clock is not stable, this bit will be set to 1. | ||
0 = Clock switching success. | ||
1 = Clock switching failure. |
PWM_T::STATUS |
[0x0120] PWM0 Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | CNTMAX0 | Time-base Counter 0 Equal to 0xFFFF Latched Status |
0 = indicates the time-base counter never reached its maximum value 0xFFFF. | ||
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. | ||
[2] | CNTMAX2 | Time-base Counter 2 Equal to 0xFFFF Latched Status |
0 = indicates the time-base counter never reached its maximum value 0xFFFF. | ||
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. | ||
[4] | CNTMAX4 | Time-base Counter 4 Equal to 0xFFFF Latched Status |
0 = indicates the time-base counter never reached its maximum value 0xFFFF. | ||
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. | ||
[21:16] | ADCTRGn | ADC Start of Conversion Status |
Each bit n controls the corresponding PWM0 channel n. | ||
0 = Indicates no ADC start of conversion trigger event has occurred. | ||
1 = Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
WDT_T::STATUS |
[0x0008] Watchdog Timer Interrupt Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | WDT_IS | Watchdog Timer Time-out Interrupt Status |
If the Watchdog timer time-out interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer time-out interrupt has occurred | ||
If the Watchdog timer time-out interrupt is not enabled, then this bit indicates that a time-out period has elapsed. | ||
0 = Watchdog timer time-out interrupt did not occur. | ||
1 = Watchdog timer time-out interrupt occurred. | ||
Note: This bit is read only, but can be cleared by writing 1 to it. | ||
[1] | WDT_RST_IS | Watchdog Timer Reset Status |
When the Watchdog timer initiates a reset, the hardware will set this bit | ||
This flag can be read by software to determine the source of reset | ||
Software is responsible to clear it manually by writing 1 to it | ||
If WTRE is disabled, then the Watchdog timer has no effect on this bit. | ||
0 = Watchdog timer reset did not occur. | ||
1 = Watchdog timer reset occurred. | ||
Note: This bit is read only, but can be cleared by writing 1 to it. | ||
[2] | WDT_WAKE_IS | Watchdog Timer Wake-up Status |
If Watchdog timer causes system to wake up from Power-down mode, this bit will be set to 1 | ||
It must be cleared by software with a write 1 to this bit. | ||
0 = Watchdog timer does not cause system wake-up. | ||
1 = Wake system up from Power-down mode by Watchdog time-out. | ||
Note1: When system in Power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS. | ||
Note2: After one engine clock, this bit can be cleared by writing 1 to it |
WWDT_T::STATUS |
[0x000c] Window Watchdog Timer Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | WWDTIF | WWDT Compare Match Interrupt Flag |
When WWCMP matches the WWDT counter, this bit is set to 1 | ||
This bit can be cleared by writing '1' to it. | ||
[1] | WWDTRF | WWDT Reset Flag |
When the WWDT counter down counts to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1 | ||
This bit can be cleared by writing '1' to it. |
SC_T::STATUS |
[0x0020] SC Transfer Status Register.
Bits | Field | Descriptions |
---|---|---|
[0] | RXOV | RX Overflow Error Status Flag (Read Only) |
This bit is set when RX buffer overflow. | ||
If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
[1] | RXEMPTY | Receiver Buffer Empty Status Flag(Read Only) |
This bit indicates RX buffer empty or not. | ||
When the last byte of Rx buffer has been read by CPU, hardware sets this bit high | ||
It will be cleared when SC receives any new data. | ||
[2] | RXFULL | Receiver Buffer Full Status Flag (Read Only) |
This bit indicates RX buffer full or not. | ||
This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. | ||
[4] | PEF | Receiver Parity Error Status Flag (Read Only) |
This bit is set to logic 1 whenever the received character does not have a valid parity bit. | ||
Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
[5] | FEF | Receiver Frame Error Status Flag (Read Only) |
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). | ||
Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
[6] | BEF | Receiver Break Error Status Flag (Read Only) |
This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). | ||
Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
[8] | TXOV | TX Overflow Error Interrupt Status Flag (Read Only) |
If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to 1 by hardware. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
[9] | TXEMPTY | Transmit Buffer Empty Status Flag (Read Only) |
This bit indicates TX buffer empty or not. | ||
When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high | ||
It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty). | ||
[10] | TXFULL | Transmit Buffer Full Status Flag (Read Only) |
This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. | ||
[17:16] | RXPOINT | Receiver Buffer Pointer Status Flag (Read Only) |
This field indicates the RX buffer pointer status flag | ||
When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one | ||
When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one. | ||
[21] | RXRERR | Receiver Retry Error (Read Only) |
This bit is set by hardware when RX has any error and retries transfer. | ||
Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
Note2 This bit is a flag and cannot generate any interrupt to CPU. | ||
Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). | ||
[22] | RXOVERR | Receiver over Retry Error (Read Only) |
This bit is set by hardware when RX transfer error retry over retry number limit. | ||
Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). | ||
[23] | RXACT | Receiver in Active Status Flag (Read Only) |
This bit is set by hardware when RX transfer is in active. | ||
This bit is cleared automatically when RX transfer is finished. | ||
[25:24] | TXPOINT | Transmit Buffer Pointer Status Flag (Read Only) |
This field indicates the TX buffer pointer status flag | ||
When CPU writes data into SC_DAT, TXPOINT increases one | ||
When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one. | ||
[29] | TXRERR | Transmitter Retry Error (Read Only) |
This bit is set by hardware when transmitter re-transmits. | ||
Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
Note2 This bit is a flag and cannot generate any interrupt to CPU. | ||
[30] | TXOVERR | Transmitter over Retry Error (Read Only) |
This bit is set by hardware when transmitter re-transmits over retry number limitation. | ||
Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
[31] | TXACT | Transmit in Active Status Flag (Read Only) |
0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed. | ||
1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted. |
I2C_T::STATUS |
[0x0008] I2C Status Register
Bits | Field | Descriptions |
---|---|---|
[7:0] | STATUS | I2C Status Bits (Read Only) |
The three least significant bits are always 0 | ||
The five most significant bits contain the status code | ||
There are 28 possible status codes | ||
When the content of I2C_STATUS is F8H, no serial interrupt is requested | ||
Other I2C_STATUS values correspond to defined I2C states | ||
When each of these states is entered, a status interrupt is requested (INTSTS = 1) | ||
A valid status code is present in I2C_STATUS one cycle after INTSTS is set by hardware and is still present one cycle after INTSTS has been reset by software | ||
In addition, states 00H stands for a Bus Error | ||
A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame | ||
Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. |
SPI_T::STATUS |
[0x0004] SPI Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) |
0 = Received data FIFO is not empty in the FIFO mode. | ||
1 = Received data FIFO is empty in the FIFO mode. | ||
[1] | RXFULL | Receive FIFO Buffer Full Indicator (Read Only) |
0 = Received data FIFO is not full in FIFO mode. | ||
1 = Received data FIFO is full in the FIFO mode. | ||
[2] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) |
0 = Transmitted data FIFO is not empty in the FIFO mode. | ||
1 =Transmitted data FIFO is empty in the FIFO mode. | ||
[3] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) |
0 = Transmitted data FIFO is not full in the FIFO mode. | ||
1 = Transmitted data FIFO is full in the FIFO mode. | ||
[4] | LTRIGF | Level Trigger Accomplish Flag (Read Only) |
In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. | ||
0 = The transferred bit length of one transaction does not meet the specified requirement. | ||
1 = The transferred bit length meets the specified requirement which defined in DWIDTH. | ||
Note: This bit is READ only | ||
As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period | ||
In FIFO mode, this bit is unmeaning. | ||
[6] | SLVSTAIF | Slave Start Interrupt Flag |
It is used to dedicate that the transfer has started in Slave mode with no slave select. | ||
0 = Slave started transfer no active. | ||
1 = Transfer has started in Slave mode with no slave select | ||
It is automatically cleared by transfer done or writing '1'. | ||
[7] | UNITIF | Unit Transfer Interrupt Flag |
0 = No transaction has been finished since this bit was cleared to 0. | ||
1 = SPI controller has finished one unit transfer. | ||
Note 1: This bit will be cleared by writing 1 to it. | ||
0 = Transfer is not finished yet. | ||
1 = Transfer is done. The interrupt is requested when the UNITIEN (SPI_CTL[17]) bit is enabled. | ||
Note 2: This bit can be cleared by writing 1 to it. | ||
[8] | RXTHIF | RX FIFO Threshold Interrupt Flag (Read Only) |
0 = RX valid data counts small or equal than RXTH (SPI_FIFOCTL[27:24]). | ||
1 = RX valid data counts bigger than RXTH. | ||
Note: If RXTHIEN(SPI_FIFOCTL[2]) = 1 and RXTHIF = 1, SPI will generate interrupt. | ||
[9] | RXOVIF | Receive FIFO over Run Interrupt Flag |
0 = No FIFO over run. | ||
1 = Receive FIFO over run. | ||
Note 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped. | ||
Note 2: This bit will be cleared by writing 1 to it. | ||
[10] | TXTHIF | Transmit FIFO Threshold Interrupt Flag (Read Only) |
0 = TX valid data counts bigger than TXTH (SPI_FIFOCTL[31:28]). | ||
1 = TX valid data counts small or equal than TXTH. | ||
[12] | RXTOIF | Receive Time-out Interrupt Flag |
0 = There is not timeout event on the received buffer. | ||
1 = Time out event active in RX FIFO is not empty. | ||
Refer to Time Out section. | ||
Note: This bit will be cleared by writing 1 to it. | ||
[13] | SLVTOIF | Slave Time-out Interrupt Flag |
If SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur | ||
Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit. | ||
0 = Slave time-out does not occur yet. | ||
1 = Slave time-out has occurred. | ||
[15] | SLVTXSKE | Slave Mode Transmit Skew Buffer Empty Status |
This bit indicates the empty status of transmit skew buffer which is used in Slave mode. | ||
[19:16] | RXCNT | Receive FIFO Data Counts (Read Only) |
This bit field indicates the valid data count of receive FIFO buffer. | ||
[23:20] | TXCNT | Transmit FIFO Data Counts (Read Only) |
This bit field indicates the valid data count of transmit FIFO buffer. | ||
[30] | WKSSIF | Wake-up by Slave Select Interrupt Flag |
When chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1 | ||
This bit can be cleared by writing '1' to it. | ||
[31] | WKCLKIF | Wake-up by SPI Clock Interrupt Flag |
When chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1 | ||
This bit can be cleared by writing '1' to it. |
ADC_T::STATUS |
[0x0058] A/D Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | ADIF | A/D Conversion End Flag |
A status flag that indicates the end of A/D conversion, ADIF (ADC_STATUS[0]) is set to 1 at these two conditions: | ||
When A/D conversion ends in single mode | ||
When A/D conversion ends on all specified channels in scan mode. | ||
Note: This bit can be cleared to 0 by software writing 1. | ||
[1] | ADCMPF0 | A/D Compare Flag 0 |
When the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. | ||
0 = Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP0[27:16]) setting. | ||
1 = Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP0[27:16]) setting. | ||
This flag can be cleared by writing 1 to it. | ||
Note: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF0 (ADC_STATUS[1]). | ||
[2] | ADCMPF1 | A/D Compare Flag 1 |
When the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. | ||
0 = Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP1[27:16]) setting. | ||
1 = Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP1[27:16]) setting. | ||
Note: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF1 (ADC_STATUS[2]). | ||
[3] | BUSY | BUSY/IDLE (Read Only) |
0 = A/D converter is in idle state. | ||
1 = A/D converter is busy at conversion. | ||
Note: This bit is mirror of SWTRG (ADC_CTL [11]) bit. | ||
[8:4] | CHANNEL | Current Conversion Channel (Read Only) |
This filed reflects the current conversion channel when BUSY (ADC_STATUS[3]) = 1 | ||
When BUSY (ADC_STATUS[3]) = 0, it shows the number of the next converted channel. | ||
[16] | INITRDY | ADC Initial Ready by Power-up Sequence Completed |
0 = ADC not powered up after system reset. | ||
1 = ADC has been powered up since the last system reset. | ||
Note: This bit will be set after system reset occurred and automatically cleared by power-up event. |
ACMP_T::STATUS |
[0x0004] Analog Comparator Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | ACMPIF | Comparator Interrupt Flag |
This bit is set by hardware whenever the comparator 0 output changes state | ||
This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1 | ||
Note: Write 1 to clear this bit to 0. | ||
[1] | ACMPO | Comparator Output |
Synchronized to the PCLK to allow reading by software | ||
Cleared when the comparator 0 is disabled, i.e | ||
ACMPEN (ACMP_CTL0[0]) is cleared to 0. | ||
Note: This bit is read only. |
I2C_T::STATUS2 |
[0x0044] I2C Status Register 2
Bits | Field | Descriptions |
---|---|---|
[0] | WKIF | Wake-up Interrupt Flag |
0 = Wake-up flag is inactive. | ||
1 = Wake-up flag is active. | ||
Note: This bit can be cleared by writing 1 to it. | ||
[1] | OVIF | I2C Overrun Status Bit |
0 = The received buffer is not overrun when the TWOLVBUF = 1. | ||
1 = The received buffer is overrun when the TWOLVBUF = 1. | ||
Note: This bit can be cleared by writing 1 to it. | ||
[2] | URIF | I2C Under run Status Bit |
0 = The transmitted buffer is not Under run when the TWOLVBUF = 1. | ||
1 = The transmitted buffer is Under run when the TWOLVBUF = 1. | ||
Note: This bit can be cleared by writing 1 to it. | ||
[3] | WRSTSWK | I2C Read/Write Status Bit in Address Wake-up Frame |
0 = Write command is recorded on the address match wake-up frame. | ||
1 = Read command is recorded on the address match wake-up frame. | ||
[4] | FULL | I2C Two Level Buffer Full |
0 = TX buffer no full when the TWOLVBUF = 1. | ||
1 = TX buffer full when the TWOLVBUF = 1. | ||
[5] | EMPTY | I2C Two Level Buffer Empty |
0 = RX buffer is not empty when the TWOLVBUF = 1. | ||
1 = RX buffer is empty when the TWOLVBUF = 1. | ||
[6] | BUSFREE | Bus Free Status |
The bus status in the controller. | ||
0 = I2C's 'Start' condition is detected on the bus. | ||
1 = Bus is free and released by 'STOP' condition or the controller is disabled. |
PWM_T::SWBRK |
[0x00dc] PWM0 Software Brake Control Register
Bits | Field | Descriptions |
---|---|---|
[2:0] | BRKETRGn | PWM0 Edge Brake Software Trigger (Write Only) (Write Protect) |
Each bit n controls the corresponding PWM0 pair n. | ||
Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM0_INTSTS1 register. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
[10:8] | BRKLTRGn | PWM0 Level Brake Software Trigger (Write Only) (Write Protect) |
Each bit n controls the corresponding PWM0 pair n. | ||
Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM0_INTSTS1 register. | ||
Note: This register is write protected. Refer to SYS_REGLCTL register. |
RTC_T::TALM |
[0x001c] RTC Time Alarm Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | SEC | 1-Sec Time Digit of Alarm Setting (0~9) |
[6:4] | TENSEC | 10-Sec Time Digit of Alarm Setting (0~5) |
[11:8] | MIN | 1-Min Time Digit of Alarm Setting (0~9) |
[14:12] | TENMIN | 10-Min Time Digit of Alarm Setting (0~5) |
[19:16] | HR | 1-Hour Time Digit of Alarm Setting (0~9) |
[21:20] | TENHR | 10-hour Time Digit of Alarm Setting (0~2) |
When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication | ||
(If RTC_TIME[21] is 1, it indicates PM time message.)the high bit of TENHR (RTC_TIME[21]) means AM/PM indication. |
RTC_T::TAMPCTL |
[0x010c] TAMPER Pin Control Register
Bits | Field | Descriptions |
---|---|---|
[1:0] | OPMODE | IO Operation Mode |
00 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode, without pull-up resistor. | ||
01 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is output push pull mode. | ||
10 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is open drain mode. | ||
11 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode with internal pull up. | ||
[2] | DOUT | IO Output Data |
0 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output low. | ||
1 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output high. | ||
[3] | CTLSEL | IO Pin State Backup Selection |
When tamper function is disabled, TAMPER pin can be used as GPIO function | ||
User can program CTLSEL bit to decide (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register. | ||
0 =TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by GPIO module | ||
It becomes floating state when system power is turned off. | ||
1 =TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by VBAT power domain | ||
LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 | ||
I/O pin state keeps previous state after system power is turned off. | ||
Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1. |
RTC_T::TAMSK |
[0x0034] RTC Time Alarm Mask Register
Bits | Field | Descriptions |
---|---|---|
[0] | MSEC | Mask 1-Sec Time Digit of Alarm Setting (0~9) |
[1] | MTENSEC | Mask 10-Sec Time Digit of Alarm Setting (0~5) |
[2] | MMIN | Mask 1-Min Time Digit of Alarm Setting (0~9) |
[3] | MTENMIN | Mask 10-Min Time Digit of Alarm Setting (0~5) |
[4] | MHR | Mask 1-Hour Time Digit of Alarm Setting (0~9) |
[5] | MTENHR | Mask 10-Hour Time Digit of Alarm Setting (0~2) |
SYS_T::TEMPCTL |
[0x0020] Temperature Sensor Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | VTEMPEN | Temperature Sensor Enable Bit |
This bit is used to enable/disable temperature sensor function. | ||
0 = Temperature sensor function Disabled (default). | ||
1 = Temperature sensor function Enabled. |
RTC_T::TICK |
[0x0030] RTC Time Tick Register
Bits | Field | Descriptions |
---|---|---|
[2:0] | TICK | Time Tick Register |
These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. | ||
000 = Time tick is 1 second. | ||
001 = Time tick is 1/2 second. | ||
010 = Time tick is 1/4 second. | ||
011 = Time tick is 1/8 second. | ||
100 = Time tick is 1/16 second. | ||
101 = Time tick is 1/32 second. | ||
110 = Time tick is 1/64 second. | ||
111 = Time tick is 1/128 second. | ||
Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. |
RTC_T::TIME |
[0x000c] RTC Time Loading Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | SEC | 1-Sec Time Digit (0~9) |
[6:4] | TENSEC | 10-Sec Time Digit (0~5) |
[11:8] | MIN | 1-Min Time Digit (0~9) |
[14:12] | TENMIN | 10-Min Time Digit (0~5) |
[19:16] | HR | 1-Hour Time Digit (0~9) |
[21:20] | TENHR | 10-hour Time Digit (0~2) |
When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication | ||
(If RTC_TIME[21] is 1, it indicates PM time message.) the high bit of TENHR (RTC_TIME[21]) means AM/PM indication. |
SC_T::TMRCTL0 |
[0x0028] SC Internal Timer 0 Control Register.
Bits | Field | Descriptions |
---|---|---|
[23:0] | CNT | Timer 0 Counter Value (ETU Based) |
This field indicates the internal timer operation values. | ||
[27:24] | OPMODE | Timer 0 Operation Mode Selection |
This field indicates the internal 24-bit timer operation selection. | ||
Refer toTable 6.15-3 Timer Operation Mode for programming Timer0. | ||
[31] | SYNC | SYNC Flag Indicator(Read Only) |
Due to synchronization, software should check this bit when writing a new value to the SC_TMRCTL0 register. | ||
0 = Synchronizing is completion, user can write new data to SC_TMRCTL0 register. | ||
1 = Last value is synchronizing. |
SC_T::TMRCTL1 |
[0x002c] SC Internal Timer 1 Control Register.
Bits | Field | Descriptions |
---|---|---|
[7:0] | CNT | Timer 1 Counter Value (ETU Based) |
This field indicates the internal timer operation values. | ||
[27:24] | OPMODE | Timer 1 Operation Mode Selection |
This field indicates the internal 8-bit timer operation selection. | ||
Refer toTable 6.15-3 Timer Operation Mode for programming Timer1. | ||
[31] | SYNC | SYNC Flag Indicator(Read Only) |
Due to synchronization, software should check this bit when writing a new value to the SC_TMRCTL1 register. | ||
0 = Synchronizing is completion, user can write new data to SC_TMRCTL1 register. | ||
1 = Last value is synchronizing. |
SC_T::TMRCTL2 |
[0x0030] SC Internal Timer 2 Control Register.
Bits | Field | Descriptions |
---|---|---|
[7:0] | CNT | Timer 2 Counter Value (ETU Based) |
This field indicates the internal timer operation values. | ||
[27:24] | OPMODE | Timer 2 Operation Mode Selection |
This field indicates the internal 8-bit timer operation selection | ||
Refer to Table 6.15-3 Timer Operation Mode for programming Timer2. | ||
[31] | SYNC | SYNC Flag Indicator(Read Only) |
Due to synchronization, software should check this bit when writing a new value to SC_TMRCTL2 register. | ||
0 = Synchronizing is completion, user can write new data to SC_TMRCTL2 register. | ||
1 = Last value is synchronizing. |
PDMA_CH_T::TOCn |
[0x0028] PDMA channel n Time-out Counter Register
Bits | Field | Descriptions |
---|---|---|
[15:0] | TOC | PDMA Time-out Period Counter |
Each PDMA channel contains an internal counter | ||
This internal counter will reload and start counting when completing each peripheral request service | ||
The internal counter loads the value of TOC (PDAM_TOCn[15:0], n=1~4) and starts counting down when setting TOUTEN (PDMA_CTLn[12], n=1~4) | ||
PDMA will request interrupt when this internal counter reaches 0 and TOUTIEN (PDMA_INTENn[6], n=1~4) is 1 | ||
[18:16] | TPSC | PDMA Time-out Counter Clock Source Prescaler |
000 = PDMA time-out clock source is HCLK/28. | ||
001 = PDMA time-out clock source is HCLK/29. | ||
010 = PDMA time-out clock source is HCLK/210. | ||
011 = PDMA time-out clock source is HCLK/211. | ||
100 = PDMA time-out clock source is HCLK/212. | ||
101 = PDMA time-out clock source is HCLK/213. | ||
110 = PDMA time-out clock source is HCLK/214. | ||
111 = PDMA time-out clock source is HCLK/215. |
I2C_T::TOCTL |
[0x0010] I2C Time-out Control Register
Bits | Field | Descriptions |
---|---|---|
[0] | TOCEN | Time-out Counter Enable Bit |
When this bit is set to enabled and clock be stretched, the 14 bits time-out counter will start counting. | ||
0 = Time-out counter Disabled. | ||
1 = Time-out counter Enabled. | ||
[1] | TOCDIV4 | Time-out Counter Input Clock Divider by 4 |
When enabled, the time-out period is extended 4 times. | ||
0 = Time-out counter input clock divider by 4 Disabled. | ||
1 = Time-out counter input clock divider by 4 Enabled. |
UART_T::TOUT |
[0x0020] UART Time-Out Control Register.
Bits | Field | Descriptions |
---|---|---|
[8:0] | TOIC | Time-out Comparator |
The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word | ||
Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TMCTL[8:0])), a receiver time-out interrupt (RXTOIF(UART_ISR[4])) is generated if RXTOIEN (UART_IER [4]) enabled | ||
A new incoming data word or RX FIFO empty will clear RXTOIF(UART_ISR[4]) | ||
In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 | ||
So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. | ||
Note1: Fill all 0 to this field indicates to disable this function. | ||
Note2: The real time-out value is TOIC + 1. | ||
Note3: The counting clock is baud rate clock. | ||
Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to fill this field great than 0xA. | ||
[23:16] | DLY | TX Delay Time Value |
This field is used to programming the transfer delay time between the last stop bit and next start bit | ||
The unit is bit time. | ||
Note1: Fill all 0 to this field indicates to disable this function. | ||
Note2: The real delay value is DLY. | ||
Note3: The counting clock is baud rate clock. |
UART_T::TRSR |
[0x0014] UART Transfer Status Register.
Bits | Field | Descriptions |
---|---|---|
[0] | ADDRDETF | RS-485 Address Byte Detection Status Flag (Read Only) |
0 = Receiver detects a data that is not an address bit (bit 9 ='0'). | ||
1 = Receiver detects a data that is an address bit (bit 9 ='1'). | ||
Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALT_CSR[19]) is set to 1 to enable Address detection mode . | ||
Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
[1] | ABRDIF | Auto-baud Rate Interrupt (Read Only) |
This bit is set to logic 1 when auto-baud rate detect function finished. | ||
0 = No Auto- Baud Rate interrupt is generated. | ||
1= Auto-Baud Rate interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing 1 to it. | ||
[2] | ABRDTOIF | Auto-baud Rate Time-out Interrupt (Read Only) |
0 = Auto-baud rate counter is underflow. | ||
1 = Auto-baud rate counter is overflow. | ||
Note1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. | ||
Note2: This bit is read only, but can be cleared by writing 1 to it. | ||
[3] | LINTXIF | LIN TX Interrupt Flag (Read Only) |
This bit is set to logic 1 when LIN transmitted header field | ||
The header may be break field or break field + sync field or break field + sync field + PID field, it can be choose by setting LINHSEL (UART_ALT_CSR[5:4]) register. | ||
0 = No LIN Transmit interrupt is generated. | ||
1 = LIN Transmit interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing 1 to it. | ||
[4] | LINRXIF | LIN RX Interrupt Flag (Read Only) |
This bit is set to logic 1 when received LIN header field | ||
The header may be break field or break field + sync field or break field + sync field + PID field, and it can be choose by setting LINHSEL (UART_ALT_CSR[5:4]) register. | ||
0 = No LIN Rx interrupt is generated. | ||
1 = LIN Rx interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing 1 to it. | ||
[5] | BITEF | Bit Error Detect Status Flag (Read Only) |
At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BITEF will be set. | ||
When occur bit error, hardware will generate an interrupt to CPU (LININT). | ||
0 = No Bit error interrupt is generated. | ||
1 = Bit error interrupt is generated. | ||
Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
Note2: This bit is only valid when enabling the bit error detection function (BITERREN (UART_ALT_CSR[8]) = 1). | ||
[7] | RXBUSY | Receive Busy Status (Read Only) |
0 = The receiver machine stays in idle state. | ||
1 = The receiver machine stays in no Idle state. | ||
Note: The user can use this to check the busy status in receiver mode | ||
If the user want to enter the power down, this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin. | ||
[8] | SLVSYNCF | LIN RX SYNC Error Flag (Read Only) |
This bit is set to logic 1 when LIN received incorrect SYNC field. | ||
User can choose the header by setting LINHSEL (UART_ALT_CSR[5:4]) register. | ||
0 = No LIN Rx sync error is generated. | ||
1 = LIN Rx sync error is generated. | ||
Note: This bit is read only, but can be cleared by writing 1 to LINRXIF. |
SPI_T::TX0 |
[0x0020] SPI Transmit Data FIFO Register 0
Bits | Field | Descriptions |
---|---|---|
[31:0] | TX | Transmit Data Register (Write Only) |
The Data Transmit Registers hold the data to be transmitted in the next transfer | ||
The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. | ||
For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer | ||
If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer. | ||
Note: | ||
1. | ||
The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22]) is set 1 | ||
The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode | ||
SPI_TX0 shall be written first in TWOBIT mode. | ||
In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data. | ||
2. | ||
If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1 |
SPI_T::TX1 |
[0x0024] SPI Transmit Data FIFO Register 1
Bits | Field | Descriptions |
---|---|---|
[31:0] | TX | Transmit Data Register (Write Only) |
The Data Transmit Registers hold the data to be transmitted in the next transfer | ||
The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. | ||
For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer | ||
If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer. | ||
Note: | ||
1 | ||
The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22]) is set 1 | ||
The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode | ||
SPI_TX0 shall be written first in TWOBIT mode. | ||
In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data. | ||
2 | ||
If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1 |
SC_T::UARTCTL |
[0x0034] SC UART Mode Control Register.
Bits | Field | Descriptions |
---|---|---|
[0] | UARTEN | UART Mode Enable Bit |
0 = Smart Card mode. | ||
1 = UART mode. | ||
Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0. | ||
Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00. | ||
Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine. | ||
[5:4] | WLS | Word Length Selection |
00 = Word length is 8 bits. | ||
01 = Word length is 7 bits. | ||
10 = Word length is 6 bits. | ||
11 = Word length is 5 bits. | ||
Note: In smart card mode, this WLS must be '00' | ||
[6] | PBOFF | Parity Bit Disable Control |
0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. | ||
1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. | ||
Note: In smart card mode, this field must be '0' (default setting is with parity bit) | ||
[7] | OPE | Odd Parity Enable Bit |
0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
Note: This bit has effect only when PBOFF bit is '0'. |
ACMP_T::VREF |
[0x0008] Analog Comparator Reference Voltage Control Register
Bits | Field | Descriptions |
---|---|---|
[3:0] | CRVCTL | Comparator Reference Voltage Setting |
CRV = CRV source voltage * (1/6+CRVCTL/24). | ||
[4] | CRVEN | CRV Enable Bit |
0 = CRV Disabled. | ||
1 = CRV Enabled. | ||
[5] | CRVSSEL | CRV Source Voltage Selection |
0 = VDDA is selected as CRV source voltage. | ||
1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. |
RTC_T::WEEKDAY |
PWM_T::WGCTL0 |
[0x00b0] PWM0 Waveform Generation Control Register 0
Bits | Field | Descriptions |
---|---|---|
[11:0] | ZPCTLn | PWM0 Zero Point Control |
Each bit n controls the corresponding PWM0 channel n. | ||
00 = Do nothing. | ||
01 = PWM0 zero point output Low. | ||
10 = PWM0 zero point output High. | ||
11 = PWM0 zero point output Toggle. | ||
PWM0 can control output level when PWM0 counter count to zero. | ||
[27:16] | PRDPCTLn | PWM0 Period (Center) Point Control |
Each bit n controls the corresponding PWM0 channel n. | ||
00 = Do nothing. | ||
01 = PWM0 period (center) point output Low. | ||
10 = PWM0 period (center) point output High. | ||
11 = PWM0 period (center) point output Toggle. | ||
PWM0 can control output level when PWM0 counter count to (PERIODn+1). | ||
Note: This bit is center point control when PWM0 counter operating in up-down counter type. |
PWM_T::WGCTL1 |
[0x00b4] PWM0 Waveform Generation Control Register 1
Bits | Field | Descriptions |
---|---|---|
[11:0] | CMPUCTLn | PWM0 Compare Up Point Control |
Each bit n controls the corresponding PWM0 channel n. | ||
00 = Do nothing. | ||
01 = PWM0 compare up point output Low. | ||
10 = PWM0 compare up point output High. | ||
11 = PWM0 compare up point output Toggle. | ||
PWM0 can control output level when PWM0 counter up count to CMPDAT. | ||
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. | ||
[27:16] | CMPDCTLn | PWM0 Compare Down Point Control |
Each bit n controls the corresponding PWM0 channel n. | ||
00 = Do nothing. | ||
01 = PWM0 compare down point output Low. | ||
10 = PWM0 compare down point output High. | ||
11 = PWM0 compare down point output Toggle. | ||
PWM0 can control output level when PWM0 counter down count to CMPDAT. | ||
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
CLK_T::WKINTSTS |
[0x0030] Wake-up Interrupt Status
Bits | Field | Descriptions |
---|---|---|
[0] | PDWKIF | Wake-up Interrupt Status in Chip Power-down Mode |
This bit indicates that some event resumes chip from Power-down mode | ||
The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred. | ||
Write 1 to clear this bit. |
SYS_T::WKSTS |
[0x007c] System Wakeup Status Register
Bits | Field | Descriptions |
---|---|---|
[0] | ACMPWK | ACMP Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with ACMP wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[1] | I2C1WK | I2C1 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with I2C1 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[2] | I2C0WK | I2C0 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with I2C0 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[3] | TMR3WK | TMR3 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested withTMR3 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[4] | TMR2WK | TMR2 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested withTMR2 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[5] | TMR1WK | TMR1 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested withTMR1 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[6] | TMR0WK | TMR0 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested withTMR0 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[7] | WDTWK | WDT Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with WDT wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[8] | BODWK | BOD Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with BOD wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[9] | SPI3WK | SPI3 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with SPI3 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[10] | SPI2WK | SPI2 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with SPI2 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[11] | SPI1WK | SPI1 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with SPI1 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[12] | SPI0WK | SPI0 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with SPI0 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[13] | UART1WK | UART1 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with UART1 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[14] | UART0WK | UART0 Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with UART0 wakeup event | ||
This flag is cleared when Power-down mode is entered. | ||
[15] | RTCWK | RTC Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with a RTC alarm or tick time happened | ||
This flag is cleared when Power-down mode is entered. | ||
[16] | GPIOWK | GPIO Wake-up Flag (Read Only) |
This flag indicates that wakeup of device from Power-down mode was requested with GPIO wakeup event | ||
This flag is cleared when Power-down mode is entered. |
UART_T::WKUPEN |
[0x0040] UART Wake-up Enable Register.
Bits | Field | Descriptions |
---|---|---|
[0] | WKCTSEN | nCTS Wake-up Enable Bit |
When the system is in power-down mode, an external nCTS change will wake-up system from power-down mode. | ||
0 = nCTS wake-up function Disabled. | ||
1 = nCTS wake-up function Enabled. | ||
[1] | WKDATEN | Incoming Data Wake-up Enable Bit |
0 = Incoming data wake-up function Disabled. | ||
1 = Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode. | ||
Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable | ||
[2] | WKTHREN | FIFO Threshold Reach Wake-up Enable Bit |
0 = Received FIFO threshold reach wake-up function Disabled. | ||
1 = Received FIFO threshold reach wake-up function Enabled when the system is in power-down mode. | ||
Note: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K. | ||
[3] | WKTHRTOEN | FIFO Threshold Reach Time Out Wake-up Enable Bit |
0 = Received FIFO threshold no reach and time out wake-up function Disabled. | ||
1 = Received FIFO threshold no reach and time out wake-up function Enabled when the system is in power-down mode. | ||
Note: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1. | ||
[4] | WKADRMEN | RS-485 Address Match Wake-up Enable Bit |
0 = RS-485 ADD mode address match wake-up function Disabled. | ||
1 = RS-485 AAD mode address match wake-up function Enabled when the system is in power-down mode. |
UART_T::WKUPSTS |
[0x0044] UART Wake-up Status Register.
Bits | Field | Descriptions |
---|---|---|
[0] | CTSWKSTS | nCTS Wake-up Flag (Read Only) |
0 = Chip stays in power-down state. | ||
1 = Chip wake-up from power-down state by nCTS wake-up. | ||
Note1: If WKCTSEN (UART_ WKUPEN [0])is enabled, the wake-up function is generated. | ||
Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
[1] | DATWKSTS | Data Wake-up Flag (Read Only) |
This bit is set if chip wake-up from power-down state by data wake-up. | ||
0 = Chip stays in power-down state. | ||
1 = Chip wake-up from power-down state by data wake-up. | ||
Note1: If WKDATEN (UART_ WKUPEN [1]) is enabled, the wake-up function is generated. | ||
Note2: This bit is read only, but can be cleared by writing '1' to it | ||
[2] | THRWKSTS | Threshold Wake-up Flag (Read Only) |
0 = Chip stays in power-down state. | ||
1 = Chip wake-up from power-down state by FIFO threshold wake-up. | ||
Note1: If WKTHREN (UART_ WKUPEN [2])is enabled, the wake-up function is generated. | ||
Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
[3] | THRTOWKSTS | Threshold Wake-up Time Out Flag (Read Only) |
0 = Chip stays in power-down state. | ||
1 = Chip wake-up from power-down state by FIFO threshold time out wake-up. | ||
Note1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled, the wake-up function is generated. | ||
Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
[4] | ADRWKSTS | RS-485 Address Byte Detection Wake-up Flag (Read Only) |
0 = Chip stays in power-down state. | ||
1 = Chip wake-up from power-down state by Receiver detects a data that is an address bit (bit 9 ='1'). | ||
Note1: If WKADRMEN (UART_WKUPEN[4])is enabled, the wake-up function is generated. | ||
Note2: This field is used for RS-485 function mode and ADDRDEN (UART_ALT_CSR[19]) is set to 1 to enable Address detection mode . | ||
Note2: This bit is read only, but can be cleared by writing '1' to it. |