NANO103 BSP V3.01.004
The Board Support Package for Nano103 Series
clk.h
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1/**************************************************************************/
12#ifndef __CLK_H__
13#define __CLK_H__
14
15#ifdef __cplusplus
16extern "C"
17{
18#endif
19
20
34#define FREQ_36MHZ 36000000
35#define FREQ_16MHZ 16000000
36
37/********************* Bit definition of PWRCTL register **********************/
38#define CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001)
39#define CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002)
40#define CLK_PWRCTL_HIRC0_EN ((uint32_t)0x00000004)
41#define CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008)
42#define CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010)
43#define CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020)
44#define CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040)
45#define CLK_PWRCTL_HXT_HXTSLTYP ((uint32_t)0x00000100)
46#define CLK_PWRCTL_HIRC1_EN ((uint32_t)0x01000000)
47#define CLK_PWRCTL_MIRC_EN ((uint32_t)0x02000000)
48#define CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100)
50#define CLK_PWRCTL_HXT_GAIN_4M ((uint32_t)0x00000000)
51#define CLK_PWRCTL_HXT_GAIN_4M_8M ((uint32_t)0x00000400)
52#define CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000800)
53#define CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000C00)
54#define CLK_PWRCTL_HXT_GAIN_16M_24M ((uint32_t)0x00001000)
55#define CLK_PWRCTL_HXT_GAIN_24M_32M ((uint32_t)0x00001400)
56#define CLK_PWRCTL_HXT_GAIN_32M_36M ((uint32_t)0x00001800)
57#define CLK_PWRCTL_HXT_GAIN_36M ((uint32_t)0x00001C00)
59/********************* Bit definition of AHBCLK register **********************/
60#define CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001)
61#define CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002)
62#define CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004)
63#define CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010)
64#define CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020)
66/********************* Bit definition of APBCLK register **********************/
67#define CLK_APBCLK_WDT_EN ((uint32_t)0x00000001)
68#define CLK_APBCLK_RTC_EN ((uint32_t)0x00000002)
69#define CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004)
70#define CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008)
71#define CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010)
72#define CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020)
73#define CLK_APBCLK_CLKOC_EN ((uint32_t)0x00000040)
74#define CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100)
75#define CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200)
76#define CLK_APBCLK_ACMP0_EN ((uint32_t)0x00000800)
77#define CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000)
78#define CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000)
79#define CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000)
80#define CLK_APBCLK_SPI3_EN ((uint32_t)0x00008000)
81#define CLK_APBCLK_UART0_EN ((uint32_t)0x00010000)
82#define CLK_APBCLK_UART1_EN ((uint32_t)0x00020000)
83#define CLK_APBCLK_PWM0_EN ((uint32_t)0x00100000)
84#define CLK_APBCLK_ADC_EN ((uint32_t)0x10000000)
85#define CLK_APBCLK_SC0_EN ((uint32_t)0x40000000)
86#define CLK_APBCLK_SC1_EN ((uint32_t)0x80000000)
88/********************* Bit definition of STATUS register **********************/
89#define CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001)
90#define CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002)
91#define CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004)
92#define CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008)
93#define CLK_CLKSTATUS_HIRC0_STB ((uint32_t)0x00000010)
94#define CLK_CLKSTATUS_HIRC1_STB ((uint32_t)0x00000020)
95#define CLK_CLKSTATUS_MIRC_STB ((uint32_t)0x00000040)
96#define CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080)
98/********************* Bit definition of PLLCTL register **********************/
99#define CLK_PLLCTL_PD ((uint32_t)0x00010000)
100#define CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000))
101#define CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000))
102#define CLK_PLLCTL_PLL_SRC_MIRC ((uint32_t)(0x00040000))
104#define CLK_PLL_SRC_N(x) (((x)-1)<<8)
105#define CLK_PLL_MLP(x) ((x)<<0)
106#if (__HXT == 12000000)
107#define CLK_PLLCTL_36MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(36))
108#define CLK_PLLCTL_32MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32))
109#define CLK_PLLCTL_28MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28))
110#define CLK_PLLCTL_24MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24))
111#define CLK_PLLCTL_22MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22))
112#define CLK_PLLCTL_16MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16))
113#else
114# error "The PLL pre-definitions are only valid when external crystal is 12MHz"
115#endif
116#define CLK_PLLCTL_36MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(36))
117#define CLK_PLLCTL_32MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32))
118#define CLK_PLLCTL_28MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28))
119#define CLK_PLLCTL_24MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24))
120#define CLK_PLLCTL_22MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22))
121#define CLK_PLLCTL_16MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16))
123#define CLK_PLLCTL_36MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(36))
124#define CLK_PLLCTL_32MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(32))
125#define CLK_PLLCTL_28MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(28))
126#define CLK_PLLCTL_24MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(24))
127#define CLK_PLLCTL_22MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(22))
128#define CLK_PLLCTL_16MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(16))
130#define CLK_PLLCTL_36MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(36))
131#define CLK_PLLCTL_32MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(32))
132#define CLK_PLLCTL_28MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(28))
133#define CLK_PLLCTL_24MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(24))
134#define CLK_PLLCTL_22MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(22))
135#define CLK_PLLCTL_16MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(16))
137/********************* Bit definition of CLKSEL0 register **********************/
138#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL<<CLK_CLKSEL0_HCLKSEL_Pos)
139#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL<<CLK_CLKSEL0_HCLKSEL_Pos)
140#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL<<CLK_CLKSEL0_HCLKSEL_Pos)
141#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL<<CLK_CLKSEL0_HCLKSEL_Pos)
142#define CLK_CLKSEL0_HCLKSEL_HIRC (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos)
143#define CLK_CLKSEL0_HCLKSEL_HIRC0 (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos)
144#define CLK_CLKSEL0_HCLKSEL_HIRC1 (0xCUL<<CLK_CLKSEL0_HCLKSEL_Pos)
145#define CLK_CLKSEL0_HCLKSEL_MIRC (0x5UL<<CLK_CLKSEL0_HCLKSEL_Pos)
146#define CLK_CLKSEL0_ISPSEL_HIRC (0x0UL<<CLK_CLKSEL0_ISPSEL_Pos)
147#define CLK_CLKSEL0_ISPSEL_MIRC (0x1UL<<CLK_CLKSEL0_ISPSEL_Pos)
148/********************* Bit definition of CLKSEL1 register **********************/
149#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos)
150#define CLK_CLKSEL1_UART0SEL_LXT (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos)
151#define CLK_CLKSEL1_UART0SEL_PLL (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos)
152#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos)
153#define CLK_CLKSEL1_UART0SEL_MIRC (0x4UL<<CLK_CLKSEL1_UART0SEL_Pos)
154#define CLK_CLKSEL1_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL1_PWM0SEL_Pos)
155#define CLK_CLKSEL1_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL1_PWM0SEL_Pos)
156#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)
157#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)
158#define CLK_CLKSEL1_TMR0SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)
159#define CLK_CLKSEL1_TMR0SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR0SEL_Pos)
160#define CLK_CLKSEL1_TMR0SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)
161#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)
162#define CLK_CLKSEL1_TMR0SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR0SEL_Pos)
163#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)
164#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)
165#define CLK_CLKSEL1_TMR1SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)
166#define CLK_CLKSEL1_TMR1SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR1SEL_Pos)
167#define CLK_CLKSEL1_TMR1SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)
168#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)
169#define CLK_CLKSEL1_TMR1SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR1SEL_Pos)
170#define CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)
171#define CLK_CLKSEL1_ADCSEL_LXT (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)
172#define CLK_CLKSEL1_ADCSEL_PLL (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos)
173#define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)
174#define CLK_CLKSEL1_ADCSEL_MIRC (0x4UL<<CLK_CLKSEL1_ADCSEL_Pos)
175#define CLK_CLKSEL1_ADCSEL_HCLK (0x5UL<<CLK_CLKSEL1_ADCSEL_Pos)
176#define CLK_CLKSEL1_SPI0SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI0SEL_Pos)
177#define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos)
178#define CLK_CLKSEL1_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI0SEL_Pos)
179#define CLK_CLKSEL1_SPI0SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos)
180#define CLK_CLKSEL1_SPI2SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI2SEL_Pos)
181#define CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos)
182#define CLK_CLKSEL1_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI2SEL_Pos)
183#define CLK_CLKSEL1_SPI2SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos)
184#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)
185#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)
186#define CLK_CLKSEL1_WDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)
187#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)
188#define CLK_CLKSEL1_WWDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)
189/********************* Bit definition of CLKSEL2 register **********************/
190#define CLK_CLKSEL2_UART1SEL_HXT (0x0UL<<CLK_CLKSEL2_UART1SEL_Pos)
191#define CLK_CLKSEL2_UART1SEL_LXT (0x1UL<<CLK_CLKSEL2_UART1SEL_Pos)
192#define CLK_CLKSEL2_UART1SEL_PLL (0x2UL<<CLK_CLKSEL2_UART1SEL_Pos)
193#define CLK_CLKSEL2_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART1SEL_Pos)
194#define CLK_CLKSEL2_UART1SEL_MIRC (0x4UL<<CLK_CLKSEL2_UART1SEL_Pos)
195#define CLK_CLKSEL2_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL2_CLKOSEL_Pos)
196#define CLK_CLKSEL2_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL2_CLKOSEL_Pos)
197#define CLK_CLKSEL2_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL2_CLKOSEL_Pos)
198#define CLK_CLKSEL2_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL2_CLKOSEL_Pos)
199#define CLK_CLKSEL2_CLKOSEL_MIRC (0x4UL<<CLK_CLKSEL2_CLKOSEL_Pos)
200#define CLK_CLKSEL2_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR2SEL_Pos)
201#define CLK_CLKSEL2_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR2SEL_Pos)
202#define CLK_CLKSEL2_TMR2SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR2SEL_Pos)
203#define CLK_CLKSEL2_TMR2SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR2SEL_Pos)
204#define CLK_CLKSEL2_TMR2SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR2SEL_Pos)
205#define CLK_CLKSEL2_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR2SEL_Pos)
206#define CLK_CLKSEL2_TMR2SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR2SEL_Pos)
207#define CLK_CLKSEL2_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR3SEL_Pos)
208#define CLK_CLKSEL2_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR3SEL_Pos)
209#define CLK_CLKSEL2_TMR3SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR3SEL_Pos)
210#define CLK_CLKSEL2_TMR3SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR3SEL_Pos)
211#define CLK_CLKSEL2_TMR3SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR3SEL_Pos)
212#define CLK_CLKSEL2_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR3SEL_Pos)
213#define CLK_CLKSEL2_TMR3SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR3SEL_Pos)
214#define CLK_CLKSEL2_SC0SEL_HXT (0x0UL<<CLK_CLKSEL2_SC0SEL_Pos)
215#define CLK_CLKSEL2_SC0SEL_PLL (0x1UL<<CLK_CLKSEL2_SC0SEL_Pos)
216#define CLK_CLKSEL2_SC0SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC0SEL_Pos)
217#define CLK_CLKSEL2_SC0SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC0SEL_Pos)
218#define CLK_CLKSEL2_SC0SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC0SEL_Pos)
219#define CLK_CLKSEL2_SC1SEL_HXT (0x0UL<<CLK_CLKSEL2_SC1SEL_Pos)
220#define CLK_CLKSEL2_SC1SEL_PLL (0x1UL<<CLK_CLKSEL2_SC1SEL_Pos)
221#define CLK_CLKSEL2_SC1SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC1SEL_Pos)
222#define CLK_CLKSEL2_SC1SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC1SEL_Pos)
223#define CLK_CLKSEL2_SC1SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC1SEL_Pos)
224#define CLK_CLKSEL2_SPI1SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos)
225#define CLK_CLKSEL2_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos)
226#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos)
227#define CLK_CLKSEL2_SPI1SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos)
228#define CLK_CLKSEL2_SPI3SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos)
229#define CLK_CLKSEL2_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI3SEL_Pos)
230#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos)
231#define CLK_CLKSEL2_SPI3SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI3SEL_Pos)
233/********************* Bit definition of APBDIV register **********************/
234#define CLK_APB0DIV_HCLK (0x0UL<<CLK_APBDIV_APB0DIV_Pos)
235#define CLK_APB0DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB0DIV_Pos)
236#define CLK_APB0DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB0DIV_Pos)
237#define CLK_APB0DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB0DIV_Pos)
238#define CLK_APB0DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB0DIV_Pos)
239#define CLK_APB1DIV_HCLK (0x0UL<<CLK_APBDIV_APB1DIV_Pos)
240#define CLK_APB1DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB1DIV_Pos)
241#define CLK_APB1DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB1DIV_Pos)
242#define CLK_APB1DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB1DIV_Pos)
243#define CLK_APB1DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB1DIV_Pos)
245/********************* Bit definition of CLKDIV0/CLKDIV1 register **********************/
246#define CLK_HCLK_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_HCLKDIV_Pos) & CLK_CLKDIV0_HCLKDIV_Msk) /* CLKDIV0 Setting for HCLK clock divider. It could be 1~16*/
247#define CLK_UART0_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_UART0DIV_Pos)& CLK_CLKDIV0_UART0DIV_Msk) /* CLKDIV0 Setting for UART0 clock divider. It could be 1~16*/
248#define CLK_TMR0_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR0DIV_Pos) & CLK_CLKDIV1_TMR0DIV_Msk) /* CLKDIV1 Setting for TMR0 clock divider. It could be 1~16*/
249#define CLK_TMR1_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR1DIV_Pos) & CLK_CLKDIV1_TMR1DIV_Msk) /* CLKDIV1 Setting for TMR1 clock divider. It could be 1~16*/
250#define CLK_ADC_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_ADCDIV_Pos) & CLK_CLKDIV0_ADCDIV_Msk) /* CLKDIV0 Setting for ADC clock divider. It could be 1~256*/
251#define CLK_UART1_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_UART1DIV_Pos)& CLK_CLKDIV0_UART1DIV_Msk) /* CLKDIV0 Setting for UART1 clock divider. It could be 1~16*/
252#define CLK_TMR2_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR2DIV_Pos) & CLK_CLKDIV1_TMR2DIV_Msk) /* CLKDIV1 Setting for TMR2 clock divider. It could be 1~16*/
253#define CLK_TMR3_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR3DIV_Pos) & CLK_CLKDIV1_TMR3DIV_Msk) /* CLKDIV1 Setting for TMR3 clock divider. It could be 1~16*/
254#define CLK_SC0_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_SC0DIV_Pos) & CLK_CLKDIV0_SC0DIV_Msk) /* CLKDIV0 Setting for SC0 clock divider. It could be 1~16*/
255#define CLK_SC1_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_SC1DIV_Pos) & CLK_CLKDIV1_SC1DIV_Msk) /* CLKDIV1 Setting for SC1 clock divider. It could be 1~16*/
256
257/********************* Bit definition of SysTick register **********************/
258#define CLK_CLKSEL0_STCLKSEL_HCLK (1)
259#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2)
261/********************* Bit definition of CLKOCTL register **********************/
262#define CLK_CLKO_EN ((uint32_t)0x00000010)
264/********************* Bit definition of WK_INTSTS register **********************/
265#define CLK_WK_INTSTS_IS ((uint32_t)0x00000001)
268/*---------------------------------------------------------------------------------------------------------*/
269/* MODULE constant definitions. */
270/*---------------------------------------------------------------------------------------------------------*/
271#define MODULE_APBCLK(x) ((x >>31) & 0x1)
272#define MODULE_CLKSEL(x) ((x >>29) & 0x3)
273#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
274#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
275#define MODULE_CLKDIV(x) ((x >>18) & 0x3)
276#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
277#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
278#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
279#define MODULE_NoMsk 0x0
280#define NA MODULE_NoMsk
282#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
283#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
284#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
285#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
286#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
287#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
288#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
289#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
291/*-------------------------------------------------------------------------------------------------------------------------------*/
292/* AHBCLK/APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5) */
293/*-------------------------------------------------------------------------------------------------------------------------------*/
294#define GPIO_MODULE (( 0UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0))
295#define PDMA_MODULE (( 0UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 1<<0))
296#define ISP_MODULE (( 0UL<<31)|( 0<<29)|( 1<<25)|( 4<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 2<<0))
297#define SRAM_MODULE (( 0UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 4<<0))
298#define STC_MODULE (( 0UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 5<<0))
299#define WDT_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(28<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0))
300#define WWDT_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(30<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0))
301#define RTC_MODULE (( 1UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 1<<0))
302#define TMR0_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|( 8<<20)|( 1<<18)|( 0xF<<10)|( 8<<5)|( 2<<0))
303#define TMR1_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|(12<<20)|( 1<<18)|( 0xF<<10)|(12<<5)|( 3<<0))
304#define TMR2_MODULE (( 1UL<<31)|( 2<<29)|( 7<<25)|( 8<<20)|( 1<<18)|( 0xF<<10)|(16<<5)|( 4<<0))
305#define TMR3_MODULE (( 1UL<<31)|( 2<<29)|( 7<<25)|(12<<20)|( 1<<18)|( 0xF<<10)|(20<<5)|( 5<<0))
306#define CLKO_MODULE (( 1UL<<31)|( 2<<29)|( 7<<25)|( 4<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 6<<0))
307#define I2C0_MODULE (( 1UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 8<<0))
308#define I2C1_MODULE (( 1UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 9<<0))
309#define ACMP0_MODULE (( 1UL<<31)|( 3<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(11<<0))
310#define SPI0_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(24<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(12<<0))
311#define SPI1_MODULE (( 1UL<<31)|( 2<<29)|( 3<<25)|(24<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(13<<0))
312#define SPI2_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(26<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(14<<0))
313#define SPI3_MODULE (( 1UL<<31)|( 2<<29)|( 3<<25)|(26<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(15<<0))
314#define UART0_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|( 0<<20)|( 0<<18)|( 0xF<<10)|( 8<<5)|(16<<0))
315#define UART1_MODULE (( 1UL<<31)|( 2<<29)|( 7<<25)|( 0<<20)|( 0<<18)|( 0xF<<10)|(12<<5)|(17<<0))
316#define PWM0_MODULE (( 1UL<<31)|( 1<<29)|( 1<<25)|( 4<<20)|( 3<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(20<<0))
317#define ADC_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|(19<<20)|( 0<<18)|( 0xFF<<10)|(16<<5)|(28<<0))
318#define SC0_MODULE (( 1UL<<31)|( 2<<29)|( 7<<25)|(16<<20)|( 0<<18)|( 0xF<<10)|(28<<5)|(30<<0))
319#define SC1_MODULE (( 1UL<<31)|( 2<<29)|( 7<<25)|(20<<20)|( 1<<18)|( 0xF<<10)|( 0<<5)|(31<<0))
321#define CLK_TIMEOUT_ERR (-1) /* end of group NANO103_CLK_EXPORTED_CONSTANTS */
324
325extern int32_t g_CLK_i32ErrCode;
326
330void CLK_DisableCKO(void);
331void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
332void CLK_PowerDown(void);
333void CLK_Idle(void);
334uint32_t CLK_GetHXTFreq(void);
335uint32_t CLK_GetLXTFreq(void);
336uint32_t CLK_GetHCLKFreq(void);
337uint32_t CLK_GetPCLK0Freq(void);
338uint32_t CLK_GetPCLK1Freq(void);
339uint32_t CLK_GetCPUFreq(void);
340uint32_t CLK_GetPLLClockFreq(void);
341uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
342void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
343void CLK_SetPCLK0(uint32_t u32ClkDiv);
344void CLK_SetPCLK1(uint32_t u32ClkDiv);
345void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
346void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
347void CLK_EnableXtalRC(uint32_t u32ClkMask);
348void CLK_DisableXtalRC(uint32_t u32ClkMask);
349void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
350void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
351uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
352void CLK_DisablePLL(void);
353void CLK_SysTickDelay(uint32_t us);
354void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
355void CLK_DisableSysTick(void);
356uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
357 /* end of group NANO103_CLK_EXPORTED_FUNCTIONS */
359 /* end of group NANO103_CLK_Driver */
361 /* end of group NANO103_Device_Driver */
363
364#ifdef __cplusplus
365}
366#endif
367
368#endif //__CLK_H__
369
370/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
int32_t g_CLK_i32ErrCode
Definition: clk.c:22
void CLK_Idle(void)
This function let system enter to Idle mode.
Definition: clk.c:90
void CLK_SetPCLK0(uint32_t u32ClkDiv)
This function set APB PCLK0 clock divider.
Definition: clk.c:274
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:127
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
Definition: clk.c:515
void CLK_DisableCKO(void)
This function disable frequency output function.
Definition: clk.c:33
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
Definition: clk.c:465
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:58
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
Definition: clk.c:501
void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
Definition: clk.c:596
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:657
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:114
uint32_t CLK_GetPCLK1Freq(void)
This function get PCLK1 frequency. The frequency unit is Hz.
Definition: clk.c:152
void CLK_PowerDown(void)
This function let system enter to fractal fx-2-down mode.
Definition: clk.c:76
uint32_t CLK_GetPCLK0Freq(void)
This function get PCLK0 frequency. The frequency unit is Hz.
Definition: clk.c:138
void CLK_DisablePLL(void)
This function disable PLL.
Definition: clk.c:583
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
Definition: clk.c:166
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:257
void CLK_SetPCLK1(uint32_t u32ClkDiv)
This function set APB PCLK1 clock divider.
Definition: clk.c:289
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
Definition: clk.c:429
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:636
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:381
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
Definition: clk.c:413
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:617
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 48 MHz.
Definition: clk.c:228
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:177
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:101