36 CLK->APBCLK &= (~CLK_APBCLK_CLKOCKEN_Msk);
58void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
61 CLK->CLKSEL2 = (
CLK->CLKSEL2 & (~CLK_CLKSEL2_CLKOSEL_Msk)) | u32ClkSrc;
79 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
140 uint32_t Div[]= {1,2,4,8,16,1,1,1};
154 uint32_t Div[]= {1,2,4,8,16,1,1,1};
179 uint32_t u32Freq =0, u32PLLSrc;
180 uint32_t u32SRC_N,u32PLL_M,u32PllReg;
182 u32PllReg =
CLK->PLLCTL;
218 u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
259 CLK->CLKDIV0 = (
CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | u32ClkDiv;
276 CLK->APBDIV = (
CLK->APBDIV & ~CLK_APBDIV_APB0DIV_Msk) | u32ClkDiv;
291 CLK->APBDIV = (
CLK->APBDIV & ~CLK_APBDIV_APB1DIV_Msk) | u32ClkDiv;
383 uint32_t u32tmp=0,u32sel=0,u32div=0;
388 u32tmp = *(
volatile uint32_t *)(u32div);
390 *(
volatile uint32_t *)(u32div) = u32tmp;
396 u32tmp = *(
volatile uint32_t *)(u32sel);
398 *(
volatile uint32_t *)(u32sel) = u32tmp;
415 CLK->PWRCTL |= u32ClkMask;
431 CLK->PWRCTL &= ~u32ClkMask;
517 uint32_t u32PllCr,u32PLL_N,u32PLL_M,u32PLLReg;
526 CLK->PLLCTL = (
CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC);
556 u32PLL_N=u32PllCr/1000000;
557 u32PLL_M=u32PllFreq/1000000;
560 if(u32PLL_M<=48 && u32PLL_N<=36 )
break;
574 CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
599 SysTick->VAL = (0x00);
600 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
603 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
621 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
624 SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
626 SysTick->LOAD = u32Count;
628 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
660 uint32_t u32Ret = 1U;
663 while((
CLK->STATUS & u32ClkMask) != u32ClkMask)
665 if(--u32TimeOutCnt == 0)
672 if(u32TimeOutCnt == 0)
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
#define CLK_CLKSEL0_STCLKSEL_HCLK
#define CLK_PLLCTL_PLL_SRC_HXT
#define CLK_PWRCTL_HXT_EN
#define CLK_PWRCTL_HIRC1_EN
#define MODULE_CLKSEL_Msk(x)
#define CLK_CLKSEL0_HCLKSEL_PLL
#define CLK_PLLCTL_PLL_SRC_HIRC
#define MODULE_CLKSEL_Pos(x)
#define CLK_HCLK_CLK_DIVIDER(x)
#define MODULE_CLKDIV_Pos(x)
#define MODULE_IP_EN_Pos(x)
#define MODULE_CLKDIV_Msk(x)
#define CLK_PWRCTL_LXT_EN
#define CLK_PLLCTL_PLL_SRC_MIRC
#define CLK_PWRCTL_HIRC0_EN
void CLK_Idle(void)
This function let system enter to Idle mode.
void CLK_SetPCLK0(uint32_t u32ClkDiv)
This function set APB PCLK0 clock divider.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
void CLK_DisableCKO(void)
This function disable frequency output function.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
uint32_t CLK_GetPCLK1Freq(void)
This function get PCLK1 frequency. The frequency unit is Hz.
void CLK_PowerDown(void)
This function let system enter to fractal fx-2-down mode.
uint32_t CLK_GetPCLK0Freq(void)
This function get PCLK0 frequency. The frequency unit is Hz.
void CLK_DisablePLL(void)
This function disable PLL.
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
void CLK_SetPCLK1(uint32_t u32ClkDiv)
This function set APB PCLK1 clock divider.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
void CLK_DisableSysTick(void)
Disable System Tick counter.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 48 MHz.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
#define CLK_PLLCTL_INDIV_Pos
#define CLK_PLLCTL_PLLSRC_Msk
#define CLK_STATUS_PLLSTB_Msk
#define CLK_PWRCTL_PDEN_Msk
#define CLK_APBDIV_APB0DIV_Msk
#define CLK_CLKOCTL_CLKOEN_Msk
#define CLK_PLLCTL_INDIV_Msk
#define CLK_CLKSEL0_HCLKSEL_Msk
#define CLK_PLLCTL_PD_Msk
#define CLK_PLLCTL_PLLMLP_Pos
#define CLK_PWRCTL_PDWKDLY_Msk
#define CLK_APBDIV_APB1DIV_Msk
#define CLK_APBCLK_CLKOCKEN_Msk
#define CLK_PWRCTL_HIRC0FSEL_Msk
#define CLK_CLKOCTL_DIV1EN_Pos
#define CLK_PLLCTL_PLLMLP_Msk
#define CLK_CLKSEL0_HIRCSEL_Msk
#define CLK
Pointer to CLK register structure.
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from CPU registers.