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MINI55_BSP V3.02.004
The Board Support Package for Mini55 Series MCU
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Modules | |
PWM Exported Functions | |
Macros | |
#define | PWM_CHANNEL_NUM (6) |
#define | PWM_CLK_DIV_1 (4UL) |
#define | PWM_CLK_DIV_2 (0UL) |
#define | PWM_CLK_DIV_4 (1UL) |
#define | PWM_CLK_DIV_8 (2UL) |
#define | PWM_CLK_DIV_16 (3UL) |
#define | PWM_EDGE_ALIGNED (0UL) |
#define | PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk) |
#define | PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk |
#define | PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk |
#define | PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk |
#define | PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk |
#define | PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk) |
#define | PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk) |
#define | PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk) |
#define | PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk) |
#define | PWM_PERIOD_INT_UNDERFLOW (0) |
#define | PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk) |
#define | PWM_CH0 0x0 |
#define | PWM_CH1 0x1 |
#define | PWM_CH2 0x2 |
#define | PWM_CH3 0x3 |
#define | PWM_CH4 0x4 |
#define | PWM_CH5 0x5 |
#define PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk) |
#define PWM_EDGE_ALIGNED (0UL) |
#define PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk) |
#define PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk) |
#define PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk) |
#define PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk) |
#define PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk) |
#define PWM_PERIOD_INT_UNDERFLOW (0) |
#define PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk |
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk |
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk |
#define PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk |