38 #define CLK_PWRCON_XTL12M 0x01UL 39 #define CLK_PWRCON_HXT 0x01UL 40 #define CLK_PWRCON_XTL32K 0x02UL 41 #define CLK_PWRCON_LXT 0x02UL 46 #define CLK_CLKSEL0_HCLK_S_XTAL 0x00UL 47 #define CLK_CLKSEL0_HCLK_S_IRC10K 0x03UL 48 #define CLK_CLKSEL0_HCLK_S_LIRC 0x03UL 49 #define CLK_CLKSEL0_HCLK_S_IRC22M 0x07UL 50 #define CLK_CLKSEL0_HCLK_S_HIRC 0x07UL 51 #define CLK_CLKSEL0_STCLK_S_XTAL 0x00UL 52 #define CLK_CLKSEL0_STCLK_S_XTAL_DIV2 0x10UL 53 #define CLK_CLKSEL0_STCLK_S_HCLK_DIV2 0x18UL 54 #define CLK_CLKSEL0_STCLK_S_IRC22M_DIV2 0x38UL 55 #define CLK_CLKSEL0_STCLK_S_HIRC_DIV2 0x38UL 56 #define CLK_CLKSEL0_STCLK_S_HCLK 0x08UL 62 #define CLK_CLKSEL1_WDT_S_XTAL 0x00000000UL 63 #define CLK_CLKSEL1_WDT_S_HCLK_DIV2048 0x00000002UL 64 #define CLK_CLKSEL1_WDT_S_IRC10K 0x00000003UL 65 #define CLK_CLKSEL1_WDT_S_LIRC 0x00000003UL 66 #define CLK_CLKSEL1_ADC_S_XTAL 0x00000000UL 67 #define CLK_CLKSEL1_ADC_S_HCLK 0x00000008UL 68 #define CLK_CLKSEL1_ADC_S_IRC22M 0x0000000CUL 69 #define CLK_CLKSEL1_ADC_S_HIRC 0x0000000CUL 70 #define CLK_CLKSEL1_SPI_S_HXTorLXT 0x00000000UL 71 #define CLK_CLKSEL1_SPI_S_HCLK 0x00000010UL 72 #define CLK_CLKSEL1_TMR0_S_XTAL 0x00000000UL 73 #define CLK_CLKSEL1_TMR0_S_IRC10K 0x00000100UL 74 #define CLK_CLKSEL1_TMR0_S_LIRC 0x00000100UL 75 #define CLK_CLKSEL1_TMR0_S_HCLK 0x00000200UL 76 #define CLK_CLKSEL1_TMR0_S_IRC22M 0x00000700UL 77 #define CLK_CLKSEL1_TMR0_S_HIRC 0x00000700UL 78 #define CLK_CLKSEL1_TMR1_S_XTAL 0x00000000UL 79 #define CLK_CLKSEL1_TMR1_S_IRC10K 0x00001000UL 80 #define CLK_CLKSEL1_TMR1_S_LIRC 0x00001000UL 81 #define CLK_CLKSEL1_TMR1_S_HCLK 0x00002000UL 82 #define CLK_CLKSEL1_TMR1_S_IRC22M 0x00007000UL 83 #define CLK_CLKSEL1_TMR1_S_HIRC 0x00007000UL 84 #define CLK_CLKSEL1_UART_S_XTAL 0x00000000UL 85 #define CLK_CLKSEL1_UART_S_IRC22M 0x02000000UL 86 #define CLK_CLKSEL1_UART_S_HIRC 0x02000000UL 87 #define CLK_CLKSEL1_PWM01_S_HCLK 0x20000000UL 88 #define CLK_CLKSEL1_PWM23_S_HCLK 0x80000000UL 94 #define CLK_CLKSEL2_FRQDIV_XTAL 0x00000000UL 95 #define CLK_CLKSEL2_FRQDIV_HXT 0x00000000UL 96 #define CLK_CLKSEL2_FRQDIV_LXT 0x00000000UL 97 #define CLK_CLKSEL2_FRQDIV_HCLK 0x00000008UL 98 #define CLK_CLKSEL2_FRQDIV_IRC22M 0x0000000CUL 99 #define CLK_CLKSEL2_FRQDIV_HIRC 0x0000000CUL 100 #define CLK_CLKSEL2_PWM45_S_HCLK 0x00000020UL 106 #define CLK_CLKDIV_ADC(x) (((x)-1) << 16) 107 #define CLK_CLKDIV_UART(x) (((x)-1) << 8) 108 #define CLK_CLKDIV_HCLK(x) ((x)-1) 113 #define MODULE_APBCLK(x) ((x >>31) & 0x1) 114 #define MODULE_CLKSEL(x) ((x >>29) & 0x3) 115 #define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) 116 #define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) 117 #define MODULE_CLKDIV(x) ((x >>18) & 0x3) 118 #define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) 119 #define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) 120 #define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) 121 #define MODULE_NoMsk 0x0 122 #define NA MODULE_NoMsk 124 #define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) 125 #define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) 126 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) 127 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) 128 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) 129 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) 130 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) 131 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) 135 #define WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDT_EN_Pos ) 136 #define TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0_EN_Pos) 137 #define TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1_EN_Pos) 138 #define FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_FDIV_EN_Pos) 139 #define I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2C_EN_Pos) 140 #define SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPI_EN_Pos) 141 #define UART_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART_EN_Pos) 142 #define PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM01_EN_Pos) 143 #define PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM23_EN_Pos) 144 #define PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM45_EN_Pos) 145 #define ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADC_EN_Pos) 146 #define ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMP_EN_Pos) 156 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
164 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
165 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
uint32_t CLK_GetPCLKFreq(void)
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
void CLK_Idle(void)
This function let system enter to Idle mode.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
void CLK_DisableCKO(void)
This function disable frequency output function.
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
This function set SysTick clock source.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
void CLK_DisableSysTick(void)
Disable System Tick counter.